View HT66F03_4655541.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

HT66F03/ HT66F04/HT68F03/ HT68F04 Small Package Enhanced Flash Type 8-Bit MCU with EEPROM
Technical Document
* Application Note - HA0075E MCU Reset and Oscillator Circuits Application Note
Features
CPU Features
* Operating Voltage:
Peripheral Features
* Flash Program Memory: 1K14 ~ 2K15 * RAM Data Memory: 648 ~ 968 * EEPROM Memory: 648 * Watchdog Timer function * Up to 8 bidirectional I/O lines * External interrupt line shared with I/O pin * Multiple Timer Module for time measure, input
* * *
* * * * * * *
fSYS= 8MHz: 2.2V~5.5V fSYS= 12MHz: 2.7V~5.5V fSYS= 20MHz: 4.5V~5.5V Up to 0.2ms instruction cycle with 20MHz system clock at VDD=5V Power down and wake-up functions to reduce power consumption Five oscillators: External high speed xtal External 32.768kHz xtal External RC Internal high speed -- no external components Internal 32kHz -- no external components Multi-mode operation: NORMAL, SLOW, IDLE and SLEEP Fully integrated internal 4MHz, 8MHz and 12MHz oscillator requires no external components All instructions executed in one or two instruction cycles Table read instructions 63 powerful instructions Up to 8 subroutine nesting levels Bit manipulation instruction
* * * *
capture, compare match output, PWM output or single pulse output functions Comparator function Dual Time-Base functions for generation of fixed time interrupt signals Low voltage reset function Low voltage detect function
* Multi-channel 12-bit resolution A/D converter * Package types: 10-pin MSOP
General Description
The devices are Flash Memory type 8-bit high performance RISC architecture microcontrollers. Offering use rs t h e c onv e n i enc e of Fl a s h M e m o r y multi-programming features, these devices also include a wide range of functions and features. Other memory includes an area of RAM Data Memory as well as an area of EEPROM memory for storage of non-volatile data such as serial numbers, calibration data etc. Analog features include a multi-channel 12-bit A/D converter and a comparator functions. Multiple and extremely flexible Timer Modules provide timing, pulse generation and PWM generation functions. Protective features such as an internal Watchdog Timer, Low Voltage Reset and Low Voltage Detector coupled with excellent noise immunity and ESD protection ensure that reliable operation is maintained in hostile electrical environments. A full choice of HXT, LXT, ERC, HIRC and LIRC oscillator functions are provided including a fully integrated system oscillator which requires no external components for its implementation. The ability to operate and switch dynamically between a range of operating modes using different clock sources gives users the ability to optimise microcontroller operation and minimize power consumption. The inclusion of flexible I/O programming features, Time-Base functions along with many other features ensure that the devices will find excellent use in applications such as electronic metering, environmental monitoring, handheld instruments, household appliances, electronically controlled tools, motor driving in addition to many others.
Rev. 1.00
1
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
Selection Table
Most features are common to all devices, the main feature distinguishing them are Memory capacity, I/O count, TM features, stack capacity and package types. The following table summarises the main features of each device.
Part No. HT66F03 VDD 2.2V~ 5.5V 2.2V~ 5.5V 2.2V~ 5.5V 2.2V~ 5.5V Program Data Data Memory Memory EEPROM 1K14 648 648 I/O 8 Ext. Int. 1 A/D 12-bit4 Timer Module 10-bit CTM1, 10-bit STM1 10-bit CTM1, 10-bit ETM1, 10-bit STM1 10-bit CTM1, 10-bit STM1 10-bit CTM1, 10-bit STM1 Comparator 1 Stack 4 Package 10MSOP
HT66F04
2K15
968
648
8
1
12-bit4
1
8
10MSOP
HT68F03
1K14
648
648
8
1
3/4 3/4
1
4
10MSOP
HT68F04
2K15
968
648
8
1
1
8
10MSOP
Block Diagram
Low V o lta g e D e te c t Low V o lta g e R eset W a tc h d o g T im e r R eset C ir c u it 8 - b it R IS C MCU C o re In te rru p t C o n tr o lle r E x te rn a l R C /X ta l O s c illa to r s In te rn a l R C O s c illa to r
F la s h /E E P R O M P r o g r a m m in g C ir c u itr y
S ta c k
F la s h P ro g ra m M e m o ry
EEPROM D a ta M e m o ry
T im e B a s e
RAM D a ta M e m o ry
1 2 - B it A /D C o n v e rte r
C o m p a ra to r I/O T im e r M o d u le s
Rev. 1.00
2
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
Pin Assignment
P A 3 /IN T /T C K 1 /T P 0 /A N 3 P A 2 /C X /[T P 0 ]/A N 2 P A 1 /C -/A N 1 /V R E F P A 0 /C + /A N 0 VSS & AVSS 5 H T66F03 1 0 M S O P -A 4 6 3 7 2 8 1 10 9 P A 4 /T C K 0 /T P 1 P A 5 /[T P 0 ]/O S C 2 P A 6 /[T C K 0 ]/[T P 1 ]/O S C 1 P A 7 /[IN T ]/[T C K 0 ]/[T C K 1 ]/[T P 1 ]/R E S VDD & AVDD
P A 3 /IN T /T C K 1 /[T C K 2 ]/T P 0 /A N 3 1 2 3 4 5 P A 2 /C X /[T C K 2 ]/[T P 0 ]/[T P 2 B ]/A N 2 P A 1 /[T P 2 A ]/C -/A N 1 /V R E F P A 0 /[T P 2 B ]/C + /A N 0 VSS & AVSS
10 9 8 7 6 H T66F04 1 0 M S O P -A
P A 4 /T C K 0 /T P 1 P A 5 /[T C K 2 ]/[T P 0 ]/T P 2 B /O S C 2 P A 6 /[T C K 0 ]/[T P 1 ]/T P 2 A /O S C 1 P A 7 /[IN T ]/[T C K 0 ]/[T C K 1 ]/[T P 1 ]/[T P 2 A ]/R E S VDD & AVDD
P A 3 /IN T /T C K 1 /T P 0 P A 2 /C X /[T P 0 ] P A 1 /C P A 0 /C + VSS 5 4 3 2
1
10 9 8 7 6
P A 4 /T C K 0 /T P 1 P A 5 /[T P 0 ]/O S C 2 P A 6 /[T C K 0 ]/[T P 1 ]/O S C 1 P A 7 /[IN T ]/[T C K 0 ]/[T C K 1 ]/[T P 1 ]/R E S VDD
H T 6 8 F 0 3 /H T 6 8 F 0 4 1 0 M S O P -A
Note:
1. Bracketed pin names indicate non-default pinout remapping locations. 2. If the pin-shared pin functions have multiple outputs simultaneously, its pin names at the right side of the / sign can be used for higher priority. 3. VDD&AVDD means the VDD and AVDD are the double bonding.
Rev. 1.00
3
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
Pin Description
With the exception of the power pins, all pins on these devices can be referenced by their Port name, e.g. PA.0, PA.1 etc, which refer to the digital I/O function of the pins. However these Port pins are also shared with other function such as the Analog to Digital Converter, Serial Port pins etc. The function of each pin is listed in the following table, however the details behind how each pin is configured is contained in other sections of the datasheet. The following tables only include the pins which are directly related to the MCU. The pin descriptions of the additional peripheral functions are located at the end of the datasheet along with the relevant peripheral function functional description. HT66F03 Pin Name PA0~PA7 AN0~AN3 VREF CC+ CX TCK0 TCK1 TP0 TP1 INT OSC1 OSC2 RES VDD AVDD VSS AVSS Note: Port A A/D converter input A/D converter reference input Comparator input Comparator input Comparator output TM0 input TM1 input TM0 I/O TM1 I/O External Interrupt HXT/ERC/LXT pin HXT/LXT pin Reset pin Power supply * A/D converter power supply * Ground ** A/D converter ground ** I/T: Input type; O/T: Output type OP: Optional by configuration option (CO) or register option PWR: Power; CO: Configuration option; ST: Schmitt Trigger input CMOS: CMOS output; NMOS: NMOS output SCOM: Software controlled LCD COM; AN: Analog input pin HXT: High frequency crystal oscillator LXT: Low frequency crystal oscillator *: VDD is the device power supply while AVDD is the ADC power supply. The AVDD pin is bonded together internally with VDD. **: VSS is the device ground pin while AVSS is the ADC ground pin. The AVSS pin is bonded together internally with VSS. PRM PRM PRM PRM 3/4 CO CO CO 3/4 3/4 3/4 3/4 CPC Function OP PAWU PAPU ACERL ADCR1 I/T ST AN AN AN AN 3/4 ST ST ST ST ST HXT LXT 3/4 ST PWR PWR PWR PWR O/T CMOS 3/4 3/4 3/4 3/4 CMOS 3/4 3/4 CMOS CMOS 3/4 3/4 HXT LXT 3/4 3/4 3/4 3/4 3/4 Pin-Shared Mapping 3/4 PA0~PA3 PA1 PA1 PA0 PA2 PA4, PA6 or PA7 PA3 or PA7 PA3, PA5 or PA2 PA4, PA6 or PA7 PA3 or PA7 PA6 PA5 PA7 3/4 3/4 3/4 3/4
Rev. 1.00
4
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
HT66F04 Pin Name PA0~PA7 AN0~AN3 VREF CC+ CX TCK0 TCK1 TCK2 TP0 TP1 TP2A TP2B INT OSC1 OSC2 RES VDD AVDD VSS AVSS Note: Port A A/D converter input A/D converter reference input Comparator input Comparator input Comparator output TM0 input TM1 input TM2 input TM0 I/O TM1 I/O TM2 I/O TM2 I/O External Interrupt HXT/ERC/LXT pin HXT/LXT pin Reset pin Power supply * A/D converter power supply * Ground ** A/D converter ground ** I/T: Input type; O/T: Output type OP: Optional by configuration option (CO) or register option PWR: Power; CO: Configuration option; ST: Schmitt Trigger input CMOS: CMOS output; NMOS: NMOS output SCOM: Software controlled LCD COM; AN: Analog input pin HXT: High frequency crystal oscillator LXT: Low frequency crystal oscillator *: VDD is the device power supply while AVDD is the ADC power supply. The AVDD pin is bonded together internally with VDD. **: VSS is the device ground pin while AVSS is the ADC ground pin. The AVSS pin is bonded together internally with VSS. PRM PRM PRM PRM PRM PRM PRM 3/4 CO CO CO 3/4 3/4 3/4 3/4 CPC Function OP PAWU PAPU ACERL ADCR1 I/T ST AN AN AN AN 3/4 ST ST ST ST ST ST ST ST HXT LXT 3/4 ST PWR PWR PWR PWR O/T CMOS 3/4 3/4 3/4 3/4 CMOS 3/4 3/4 3/4 CMOS CMOS CMOS CMOS 3/4 3/4 HXT LXT 3/4 3/4 3/4 3/4 3/4 Pin-Shared Mapping 3/4 PA0~PA3 PA1 PA1 PA0 PA2 PA4, PA6 or PA7 PA3 or PA7 PA3, PA5 or PA2 PA3, PA5 or PA2 PA4, PA6 or PA7 PA6, PA1 or PA7 PA5, PA0 or PA2 PA3 or PA7 PA6 PA5 PA7 3/4 3/4 3/4 3/4
Rev. 1.00
5
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
HT68F03/HT68F04 Pin Name PA0~PA7 CC+ CX TCK0 TCK1 TP0 TP1 INT OSC1 OSC2 RES VDD VSS Note: Port A Comparator input Comparator input Comparator output TM0 input TM1 input TM0 I/O TM1 I/O External Interrupt HXT/ERC/LXT pin HXT/LXT pin Reset pin Power supply Ground I/T: Input type; O/T: Output type OP: Optional by configuration option (CO) or register option PWR: Power; CO: Configuration option; ST: Schmitt Trigger input CMOS: CMOS output; NMOS: NMOS output SCOM: Software controlled LCD COM; AN: Analog input pin HXT: High frequency crystal oscillator LXT: Low frequency crystal oscillator PRM PRM PRM PRM PRM CO CO CO 3/4 3/4 CPC CPC Function OP PAWU PAPU I/T ST AN AN 3/4 ST ST ST ST ST HXT LXT 3/4 ST PWR PWR O/T CMOS 3/4 3/4 CMOS 3/4 3/4 CMOS CMOS 3/4 3/4 HXT LXT 3/4 3/4 3/4 Pin-Shared Mapping 3/4 PA1 PA0 PA2 PA4, PA6 or PA7 PA3 or PA7 PA3, PA5 or PA2 PA4, PA6 or PA7 PA3 or PA7 PA6 PA5 PA7 3/4 3/4
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V Input Voltage..............................VSS-0.3V to VDD+0.3V IOL Total ................................................................80mA Total Power Dissipation .....................................500mW Storage Temperature ............................-50C to 125C Operating Temperature...........................-40C to 85C IOH Total..............................................................-80mA
Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
Rev. 1.00
6
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
D.C. Characteristics
Test Conditions Symbol Parameter VDD Operating Voltage (HXT, ERC, HIRC) Conditions fSYS=8MHz VDD 3/4 fSYS=12MHz fSYS=20MHz 3V 5V 3V 5V IDD1 Operating Current (HXT), (fSYS=fH, fS=fSUB=fLIRC) 3V 5V 3V 5V 5V 3V 5V 3V IDD2 Operating Current (ERC), (fSYS=fH, fS=fSUB=fLIRC) 5V 3V 5V 5V 3V 5V IDD3 Operating Current (HIRC), (fSYS=fH, fS=fSUB=fLXR or fLIRC) 3V 5V 3V 5V No load, fH=8MHz, ADC off, WDT enable No load, fH=10MHz, ADC off, WDT enable No load, fH=12MHz, ADC off, WDT enable No load, fH=16MHz, ADC off, WDT enable No load, fH=20MHz, ADC off, WDT enable No load, fH=6MHz, ADC off, WDT enable No load, fH=8MHz, ADC off, WDT enable No load, fH=12MHz, ADC off, WDT enable No load, fH=16MHz, ADC off, WDT enable No load, fH=4MHz, ADC off, WDT enable No load, fH=8MHz, ADC off, WDT enable No load, fH=12MHz, ADC off, WDT enable 2.2 2.7 4.5 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 1.0 2.5 1.2 2.8 1.5 3.5 2.0 4.5 5.5 0.9 2.0 1.2 2.8 1.8 4.0 5.0 0.7 1.5 1.2 2.8 1.8 4.0 5.5 5.5 5.5 1.5 4.0 2.0 4.5 2.5 5.5 3.0 7.0 8.5 1.5 3.0 2.0 4.5 3.0 6.0 7.5 1.2 2.5 2.0 4.5 3.0 6.0 V V V mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA Min. Typ. Max. Unit Ta=25C
Rev. 1.00
7
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
Ta=25C Test Conditions Symbol Parameter VDD 3V 5V 3V 5V 3V IDD4 Operating Current (HXT), (fSYS=fL, fS=fSUB=fLIRC) 5V 3V 5V 3V 5V 3V 5V 3V IDD5 Operating Current (LXT), (fSYS=fL=fLXT, fS=fSUB=fLXT) 5V 3V 5V IDD6 Operating Current (LIRC), (fSYS=fL=fLIRC, fS=fSUB=fLIRC) Operating Current (RTC), (fSYS=fL=fLXT, fS=fSUB=fLIRC) Standby Current (Idle) (HXT), (fSYS=fH, fS=fSUB=fLIRC) Standby Current (Idle) (HXT), (fSYS=off, fS=fSYS/4) Standby Current (Idle) (HXT), (fSYS=off, fS=fSUB=fLIRC) Standby Current (Idle) (HXT), (fSYS=off, fS=fSUB=fLIRC) Standby Current (Idle) (HXT), (fSYS=fL, fS=fSUB=fLIRC) Standby Current (Idle) (HXT), (fSYS=off, fS=fSUB=fLIRC) Standby Current (Idle) (LXT), (fSYS=fL=fLXT, fS=fSUB=fLXT) 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V Conditions No load, fH=12MHz, fL=fH/2, ADC off, WDT enable No load, fH=12MHz, fL=fH/4, ADC off, WDT enable No load, fH=12MHz, fL=fH/8, ADC off, WDT enable No load, fH=12MHz, fL=fH/16, ADC off, WDT enable No load, fH=12MHz, fL=fH/32, ADC off, WDT enable No load, fH=12MHz, fL=fH/64, ADC off, WDT enable No load, ADC off, WDT enable, QOSC=0 No load, ADC off, WDT enable, QOSC=1 No load, ADC off, WDT enable No load, ADC off, WDT enable, QOSC=0 No load, system HALT, ADC off, WDT enable, fSYS=12MHz No load, system HALT, ADC off, WDT enable, fSYS=12MHz No load, system HALT, ADC off, WDT enable, fSYS=12MHz No load, system HALT, ADC off, WDT enable, fSYS=12MHz No load, system HALT, ADC off, WDT enable, fSYS=12MHz/64 No load, system HALT, ADC off, WDT enable, fSYS=12MHz/64 No load, system HALT, ADC off, WDT enable, fSYS=32768Hz 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 0.90 2.50 0.70 2.00 0.60 1.60 0.50 1.50 0.49 1.45 0.47 1.40 10 30 10 40 10 30 10 40 0.6 1.2 1.3 2.2 1.3 2.2 1.3 2.2 0.6 1.3 1.3 2.2 5 16 1.50 3.75 1.00 3.00 0.90 2.40 0.75 2.25 0.74 2.18 0.71 2.10 20 50 20 60 20 50 20 60 1.0 2.0 3.0 5.0 3.0 5.0 3.0 5.0 0.9 2.0 3.0 5.0 10 32 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA Min. Typ. Max. Unit
IDD7
ISTB1
ISTB2
ISTB3
ISTB4
ISTB5
ISTB6
ISTB7
Rev. 1.00
8
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
Ta=25C Test Conditions Symbol Parameter VDD ISTB8 Standby Current (Idle) (HXT), (fSYS=off, fS=fSYS/4) Standby Current (Idle) (LXT), (fSYS=off, fS=fSUB=fLXT) Standby Current (Idle) (LIRC), (fSYS=off, fS=fSUB=fLIRC) Standby Current (Idle) (LXT), (fSYS=off, fS=fSUB=fLIRC) Standby Current (Sleep) (HXT), (fSYS=off, fS=fSUB=fLIRC) Standby Current (Sleep) (HXT), (fSYS=off, fS=fSUB=fLIRC) Standby Current (Sleep) (LXT), (fSYS=off, fS=fSUB=fLXT or fLIRC) Standby Current (Sleep) (LXT), (fSYS=off, fS=fSUB=fLXT) 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V Conditions No load, system HALT, ADC off, WDT enable, fSYS=32768Hz No load, system HALT, ADC off, WDT enable, fSYS=32768Hz No load, system HALT, ADC off, WDT enable, fSYS=32kHz No load, system HALT, ADC off, WDT enable, fSYS=32768Hz No load, system HALT, ADC off, WDT disable, fSYS=12MHz No load, system HALT, ADC off, WDT enable, fSYS=12MHz No load, system HALT, ADC off, WDT disable, fSYS=32768Hz No load, system HALT, ADC off, WDT enable, fSYS=32768Hz 3/4 3/4 3/4 3/4 LVR Enable, 2.10V option LVR Voltage Level VLVR3 VLVR4 VLVD1 VLVD2 VLVD3 VLVD4 LVD Voltage Level VLVD5 VLVD6 VLVD7 VLVD8 ILVD1 ILVD2 Additional Power Consumption 3/4 if LVR and LVD is Used 3/4 3/4 LVR Enable, 2.55V option LVR Enable, 3.15V option LVR Enable, 4.20V option LVDEN=1, VLVD=2.0V LVDEN=1, VLVD=2.2V LVDEN=1, VLVD=2.4V LVDEN=1, VLVD=2.7V LVDEN=1, VLVD=3.0V LVDEN=1, VLVD=3.3V LVDEN=1, VLVD=3.6V LVDEN=1, VLVD=4.4V LVR disable, LVDEN=1 LVR enable, LVDEN=1 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 0 0.7VDD 0 0.9VDD -5% -5% -5% -5% -5% -5% -5% -5% -5% -5% -5% -5% 3/4 3/4 5 16 5 16 1.3 2.2 1.3 2.2 0.1 0.3 1.3 2.2 0.1 0.3 5 16 3/4 3/4 3/4 3/4 2.10 2.55 3.15 4.20 2.00 2.20 2.40 2.70 3.00 3.30 3.60 4.40 75 90 10 32 10 32 3.0 5.0 3.0 5.0 1.0 2.0 5.0 10.0 1.0 2.0 10 32 0.3VDD VDD 0.4VDD VDD +5% +5% +5% +5% +5% +5% +5% +5% +5% +5% +5% +5% 120 150 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA V V V V V V V V V V V V V V V V mA mA Min. Typ. Max. Unit
ISTB9
ISTB10
ISTB11
ISTB12
ISTB13
ISTB14
ISTB15
VIL1 VIH1 VIL2 VIH2 VLVR1 VLVR2
Input Low Voltage for I/O Ports, 3/4 TCKx and INT Input High Voltage for I/O Ports, 3/4 TCKx and INT Input Low Voltage (RES) Input High Voltage (RES) 3/4 3/4
Rev. 1.00
9
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
Ta=25C Test Conditions Symbol Parameter VDD VOL 3V Output Low Voltage I/O Port 5V VOH 3V Output High Voltage I/O Port 5V RPH Pull-high Resistance for I/O Ports 1.25V Reference with Buffer Voltage 3V 5V 3/4 IOL=20mA IOH=-3.2mA IOH=-7.4mA 3/4 3/4 3/4 Conditions IOL=9mA 3/4 3/4 2.7 4.5 20 10 -3% 3/4 3/4 3/4 3/4 3/4 60 30 1.25 0.3 0.5 3/4 3/4 100 50 +3% V V V V kW kW V Min. Typ. Max. Unit
V125
I125
Additional Power Consumption if 1.25V Reference with Buffer is 3/4 used
200
300
mA
A.C. Characteristics
Test Conditions Symbol Parameter VDD Conditions 2.2V~5.5V fCPU Operating Clock 3/4 2.7V~5.5V 4.5V~5.5V 2.2V~5.5V fSYS System Clock (HXT) 3/4 2.7V~5.5V 4.5V~5.5V 5V 5V 5V fERC System Clock (ERC) Ta=25C, R=120kW * Ta=0~70C, R=120kW * Ta= -40C~85C, R=120kW * DC DC DC 0.4 0.4 0.4 -2% -5% -7% -9% -15% 3/4 3/4 3/4 3/4 3/4 3/4 8 8 8 8 8 8 12 20 8 12 20 +2% +6% +9% +10% +10% Min. Typ. Max.
Ta=25C Unit MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz
3.0V~ Ta= -40C~85C, 5.5V R=120kW * 2.2V~ Ta= -40C~85C, 5.5V R=120kW *
Rev. 1.00
10
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
Ta=25C Test Conditions Symbol Parameter VDD Conditions -2% -2% -2% -5% -5% -5% -7% -5% -6% -4% -6% -12% -10% -15% -8% -12% 3/4 2 2 2 2 -10% 3/4 3/4 (for verify) 3/4 For all VLVD, LVR disable 3/4 1 1 120 1 15 10 4 8 12 4 8 12 4 4 8 8 12 4 4 8 8 12 32768 3/4 3/4 3/4 3/4 32 3/4 3/4 240 3/4 3/4 3/4 +2% +2% +2% +5% +4% +3% +7% +9% +4% +9% +7% +8% +9% +5% +9% +7% 3/4 8 10 12 16 +10% 3/4 3/4 480 2 3/4 3/4 MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz Hz MHz MHz MHz MHz kHz ms tSYS ms tSUB ms ms 3V/5V Ta=25C 3V/5V Ta=25C 5V Ta=25C Min. Typ. Max. Unit
3V/5V Ta=0~70C 3V/5V Ta=0~70C 5V Ta=0~70C
2.2V~ Ta=0~70C 3.6V 3.0V~ Ta=0~70C 5.5V 2.2V~ Ta=0~70C 3.6V 3.0V~ Ta=0~70C 5.5V 3.0V~ Ta=0~70C 5.5V 2.2V~ Ta= -40C~85C 3.6V 3.0V~ Ta= -40C~85C 5.5V 2.2V~ Ta= -40C~85C 3.6V 3.0V~ Ta= -40C~85C 5.5V 3.0V~ Ta= -40C~85C 5.5V fLXT System Clock (LXT) 3/4 2.2~ 5.5V 2.7~ 5.5V Timer I/P Frequency (TMR) 3.3~ 5.5V 4.5~ 5.5V fLIRC tRES tINT tLVR tLVD tLVDS tBGS System Clock (LIRC) External Reset Low Pulse Width Interrupt Pulse Width Low Voltage Width to Reset Low Voltage Width to Interrupt LVDO stable time V125 Turn on Stable Time 5V 3/4 3/4 3/4 3/4 3/4 3/4 Ta=25C 3/4 3/4 3/4 3/4 3/4
fHIRC
System Clock (HIRC)
fTIMER
Rev. 1.00
11
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
Ta=25C Test Conditions Symbol Parameter VDD Conditions fSYS=XTAL or RTC OSC System Start-up Timer Period (Wake-up from HALT) fSYS=ERC or HIRC OSC 3/4 fSYS=LIRC OSC Both RTC and LIRC are off in any fSYS Note: 1. tSYS=1/fSYS 2. * For fERC, as the resistor tolerance will influence the frequency a precision resistor is recommended. 3. To maintain the accuracy of the internal HIRC oscillator frequency, a 0.1mF decoupling capacitor should be connected between VDD and VSS and located as close to the device as possible. 3/4 3/4 3/4 3/4 1024 15~16 1~2 1024 3/4 3/4 3/4 3/4 tSYS Min. Typ. Max. Unit
tSST
A/D Converter Characteristics
Test Conditions Symbol AVDD VADI VREF DNL INL IADC Parameter VDD A/D Converter Operating Voltage A/D Converter Input Voltage A/D Converter Reference Voltage Differential Non-linearity Integral Non-linearity Additional Power Consumption if A/D Converter is Used A/D Converter Clock Period A/D Conversion Time (Include Sample and Hold Time) A/D Converter Sampling Time A/D Converter On-to-Start Time 3/4 3/4 3/4 5V 5V 3V 5V 2.2~ 5.5V Conditions VREF=AVDD 3/4 3/4 tADCK= 1.0ms tADCK= 1.0ms No load, tADCK= 0.5ms No load, tADCK= 0.5ms 3/4 2.7 0 2 3/4 3/4 3/4 3/4 0.5 3/4 3/4 2 3/4 3/4 3/4 1 2 0.90 1.20 3/4 16 4 3/4 5.5 VREF AVDD 2 4 1.35 1.80 10 3/4 3/4 3/4 Min. Typ. Max.
Ta=25C Unit V V V LSB LSB mA mA ms tADCK tADCK ms
tADCK tADC tADS tON2ST
2.2~ 12-bit A/D Converter 5.5V 2.2~ 5.5V 2.2~ 5.5V 3/4 3/4
Rev. 1.00
12
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
Comparator Electrical Characteristics
Test Conditions Symbol VCMP ICMP VCMPOS VHYS VCM AOL tPD Note: Parameter VDD Comparator Operating Voltage Comparator Operating Current 5V Comparator Input Offset Voltage Hysteresis Width Comparator Common Mode Voltage Range Comparator Open Loop Gain Comparator Response Time 3/4 3/4 3/4 3/4 3/4 3/4 3V Conditions 3/4 3/4 3/4 3/4 3/4 3/4 3/4 With 100mV overdrive (Note) 2.2 3/4 3/4 -10 20 VSS 60 3/4 3/4 37 130 3/4 40 3/4 80 370 5.5 56 200 10 60 VDD-1.4V 3/4 560 V mA mA mV mV V dB ns Min. Typ. Max. Unit Ta=25C
Measured with comparator one input pin at VCM = (VDD-1.4)/2 while the other pin input transition from VSS to (VCM +100mV) or from VDD to (VCM -100mV). Ta=25C Test Conditions Min. VDD Conditions 3/4 3/4 3/4 3/4 0.035 1 3/4 3/4 3/4 100 3/4 3/4 mV V/ms ms 3/4 3/4 3/4 Typ. Max. Unit
Power-on Reset Characteristics
Symbol VPOR RPOR AC tPOR Parameter VDD Start Voltage to Ensure Power-on Reset VDD Raising Rate to Ensure Power-on Reset Minimum Time for VDD Stays at VPOR to Ensure Power-on Reset
V
DD
tP
OR
RR
VDD
V
POR
T im e
Rev. 1.00
13
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
System Architecture
A key factor in the high-performance features of the Holtek range of microcontrollers is attributed to their internal system architecture. The range of devices take advantage of the usual features found within RISC microcontrollers providing increased speed of operation and enhanced performance. The pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. An 8-bit wide ALU is used in practically all instruction set operations, which carries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. The internal data path is simplified by moving data through the Accumulator and the ALU. Certain internal registers are implemented in the Data Memory and can be directly or indirectly addressed. The simple addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional I/O and A/D control system with maximum reliability and flexibility. This makes the device suitable for low-cost, high-volume production for controller applications. Clocking and Pipelining The main system clock, derived from either a HXT, LXT, HIRC, LIRC or ERC oscillator is subdivided into four internally generated non-overlapping clocks, T1~T4. The Program Counter is incremented at the beginning of the T1 clock during which time a new instruction is fetched. The remaining T2~T4 clocks carry out the decoding and execution functions. In this way, one T1~T4 clock cycle forms one instruction cycle. Although the fetching and execution of instructions takes place in consecutive instruction cycles, the pipelining structure of the microcontroller ensures that instructions are effectively executed in one instruction cycle. The exception to this are instructions where the contents of the Program Counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. For instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. An extra cycle is required as the program takes one cycle to first obtain the actual jump or call address and then another cycle to actually execute the branch. The requirement for this extra cycle should be taken into account by programmers in timing sensitive applications.
(S y s te m
fS Y S C lo c k )
P h a s e C lo c k T 1 P h a s e C lo c k T 2 P h a s e C lo c k T 3 P h a s e C lo c k T 4 P ro g ra m C o u n te r PC PC+1 PC+2
P ip e lin in g
F e tc h In s t. (P C ) E x e c u te In s t. (P C -1 )
F e tc h In s t. (P C + 1 ) E x e c u te In s t. (P C )
F e tc h In s t. (P C + 2 ) E x e c u te In s t. (P C + 1 )
System Clocking and Pipelining
1 2 3 4 5 6 D ELAY: : :
M O V A ,[1 2 H ] C ALL D ELAY C P L [1 2 H ]
F e tc h In s t. 1
E x e c u te In s t. 1 F e tc h In s t. 2 E x e c u te In s t. 2 F e tc h In s t. 3 F lu s h P ip e lin e F e tc h In s t. 6 E x e c u te In s t. 6 F e tc h In s t. 7
NOP
Instruction Fetching
Rev. 1.00
14
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
Program Counter During program execution, the Program Counter is used to keep track of the address of the next instruction to be executed. It is automatically incremented by one each time an instruction is executed except for instructions, such as JMP or CALL that demand a jump to a non-consecutive Program Memory address. Only the lower 8 bits, known as the Program Counter Low Register, are directly addressable by the application program. When executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading the required address into the Program Counter. For conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained. Program Counter Device HT66F03 HT68F03 HT66F04 HT68F04 Program Counter High Byte PC9, PC8 PCL7~PCL0 PC10~PC8 Program Counter The lower byte of the Program Counter, known as the Program Counter Low register or PCL, is available for program control and is a readable and writeable register. By transferring data directly into this register, a short program jump can be executed directly, however, as only this low byte is available for manipulation, the jumps are limited to the present page of memory, that is 256 locations. When such program jumps are executed it should also be noted that a dummy cycle will be inserted. Manipulating the PCL register may cause program branching, so an extra cycle is needed to pre-fetch. Stack This is a special part of the memory which is used to save the contents of the Program Counter only. The stack has multiple levels depending upon the device and is neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the Stack Pointer, and is neither readable nor writeable. At a subroutine call or interrupt acknowledge signal, the contents of the Program Counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction, RET or RETI, the Program Counter is restored to its previous value from the stack. After a device reset, the Stack Pointer will point to the top of the stack. PCL Register
B o tto m o f S ta c k S ta c k L e v e l N
If the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the Stack Pointer is decremented, by RET or RETI, the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily. However, when the stack is full, a CALL subroutine instruction can still be executed which will result in a stack overflow. Precautions should be taken to avoid such cases which might cause unpredictable program branching. If the stack is overflow, the first Program Counter save in the stack will be lost.
P ro g ra m C o u n te r
T o p o f S ta c k S ta c k P o in te r
S ta c k L e v e l 1 S ta c k L e v e l 2 S ta c k L e v e l 3 P ro g ra m M e m o ry
Device HT66F03/HT68F03 HT66F04/HT68F04
Stack Levels 4 8
Arithmetic and Logic Unit - ALU The arithmetic-logic unit or ALU is a critical area of the microcontroller that carries out arithmetic and logic operations of the instruction set. Connected to the main microcontroller data bus, the ALU receives related instruction codes and performs the required arithmetic or logical operations after which the result will be placed in the specified register. As these ALU calculation or operations may result in carry, borrow or other status changes, the status register will be correspondingly updated to reflect these changes. The ALU supports the following functions:
* Arithmetic operations: ADD, ADDM, ADC, ADCM,
SUB, SUBM, SBC, SBCM, DAA
* Logic operations: AND, OR, XOR, ANDM, ORM,
XORM, CPL, CPLA
* Rotation RRA, RR, RRCA, RRC, RLA, RL, RLCA,
RLC
* Increment and Decrement INCA, INC, DECA, DEC * Branch decision, JMP, SZ, SZA, SNZ, SIZ, SDZ,
SIZA, SDZA, CALL, RET, RETI
Rev. 1.00
15
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
Flash Program Memory
The Program Memory is the location where the user code or program is stored. For this device series the Program Memory is Flash type, which means it can be programmed and re-programmed a large number of times, allowing the user the convenience of code modification on the same device. By using the appropriate programming tools, these Flash devices offer users the flexibility to conveniently debug and develop their applications while also offering a means of field programming and updating. Structure The Program Memory has a capacity of 1K14 bits to 2K15 bits. The Program Memory is addressed by the Program Counter and also contains data, table information and interrupt entries. Table data, which can be setup in any location within the Program Memory, is addressed by a separate table pointer register. Device HT66F03 HT68F03 HT66F04 HT68F04
H T66F03 H T68F03 0000H 0004H 0020H 03FFH R eset In te rru p t V e c to r 1 4 b its 07FFH 1 5 b its
TABRD[m] or TABRDL[m] instructions, respectively. When the instruction is executed, the lower order table byte from the Program Memory will be transferred to the user defined Data Memory register [m] as specified in the instruction. The higher order table data byte from the Program Memory will be transferred to the TBLH special register. Any unused bits in this transferred higher order byte will be read as 0. The accompanying diagram illustrates the addressing data flow of the look-up table.
Lastpage or T B H P R e g is te r T B L P R e g is te r P ro g ra m A d d re s s R e g is te r T B L H H ig h B y te M e m o ry D a ta 1 4 ~ 1 5 b its
U s e r S e le c te d R e g is te r Low B y te
Capacity 1K14
Table Program Example 2K15
H T66F04 H T68F04 R eset In te rru p t V e c to r
Program Memory Structure Special Vectors Within the Program Memory, certain locations are reserved for the reset and interrupts. The location 000H is reserved for use by the device reset for program initialisation. After a device reset is initiated, the program will jump to this location and begin execution. Look-up Table Any location within the Program Memory can be defined as a look-up table where programmers can store fixed data. To use the look-up table, the table pointer must first be setup by placing the address of the look up data to be retrieved in the table pointer register, TBLP and TBHP. These registers define the total address of the look-up table. After setting up the table pointer, the table data can be retrieved from the Program Memory using the
The following example shows how the table pointer and table data is defined and retrieved from the microcontroller. This example uses raw table data located in the Program Memory which is stored there using the ORG statement. The value at this ORG statement is 700H which refers to the start address of the last page within the 2K words Program Memory of the device. The table pointer is setup here to have an initial value of 06H. This will ensure that the first data read from the data table will be at the Program Memory address 706H or 6 locations after the start of the last page. Note that the value for the table pointer is referenced to the first address of the present page if the TABRD [m] instruction is being used. The high byte of the table data which in this case is equal to zero will be transferred to the TBLH register automatically when the TABRD [m] instruction is executed. Because the TBLH register is a read-only register and cannot be restored, care should be taken to ensure its protection if both the main routine and Interrupt Service Routine use table read instructions. If using the table read instructions, the Interrupt Service Routines may change the value of the TBLH and subsequently cause errors if used again by the main routine. As a rule it is recommended that simultaneous use of the table read instructions should be avoided. However, in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. Note that all table related instructions require two instruction cycles to complete their operation.
Rev. 1.00
16
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
In Circuit Programming The provision of Flash type Program Memory provides the user with a means of convenient and easy upgrades and modifications to their programs on the same device. As an additional convenience, Holtek has provided a means of programming the microcontroller in-circuit using a 5-pin interface. This provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller, and then programming or upgrading the program at a later stage. This enables product manufacturers to easily keep their manufactured products supplied with the latest program releases without removal and re-insertion of the device. MCU Programming Pins PA0 PA2 RES VDD VSS Function Serial Data Input/Output Serial Clock Device Reset Power Supply Ground The Program Memory and EEPROM data memory can both be programmed serially in-circuit using this 5-wire interface. Data is downloaded and uploaded serially on a single pin with an additional line for the clock. Two additional lines are required for the power supply and one line for the reset. The technical details regarding the in-circuit programming of the devices are beyond the scope of this document and will be supplied in supplementary literature. During the programming process the RES pin will be held low by the programmer disabling the normal operation of the microcontroller and taking control of the PA0 and PA2 I/O pins for data and clock programming purposes. The user must there take care to ensure that no other outputs are connected to these two pins.
* Table Read Program Example tempreg1 db ? ; temporary register #1 tempreg2 db ? ; temporary register #2 : : mov a,06h ; initialise low table pointer - note that this address mov tblp,a ; is referenced mov a,07h ; initialise high table pointer tbhp,a : : tabrd tempreg1 ; transfers value in table referenced by table pointer data at program ; memory address 706H transferred to tempreg1 and TBLH
dec tblp tabrd tempreg2
; reduce value of table pointer by one ; ; ; ; transfers value in table referenced by table pointer data at program memory address 705H transferred to tempreg2 and TBLH in this example the data 1AH is transferred to tempreg1 and data 0FH to register tempreg2
: : org 700h
; sets initial address of program memory
dc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh : :
Rev. 1.00
17
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
W r ite r C o n n e c to r S ig n a ls W r ite r _ V D D MCU VDD P r o g r a m m in g P in s
Device HT66F03 HT68F03 HT66F04 HT68F04
Capacity 648 968
Bank 0 40H~7FH 40H~9FH
Bank 1 40H (EEC) available only 40H (EEC) available only
RES DATA
RES DATA
CLK
CLK
The second area of Data Memory is known as the General Purpose Data Memory, which is reserved for general purpose use. All locations within this area are read and write accessible under program control. The overall Data Memory is subdivided into two banks for all the devices. The Special Purpose Data Memory registers are accessible in all banks, with the exception of the EEC register at address 40H, which is only accessible in Bank 1. Switching between the different Data Memory banks is achieved by setting the Bank Pointer to the correct value. The start address of the Data Memory for all devices is the address 00H.
W r ite r _ V S S * * *
VSS
T o o th e r C ir c u it
Note:
* may be resistor or capacitor. The resistance of * must be greater than 1kW or the capacitance of * must be less than 1nF.
Programmer Pin RES DATA CLK
MCU Pins PA7 PA0 PA2
Programmer and MCU Pins
RAM Data Memory
The Data Memory is a volatile area of 8-bit wide RAM internal memory and is the location where temporary information is stored. Structure Divided into two sections, the first of these is an area of RAM, known as the Special Function Data Memory. Here are located registers which are necessary for correct operation of the device. Many of these registers can be read from and written to directly under program control, however, some remain protected from user manipulation.
00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH
Bank 0 & Bank 1 IA R 0 MP0 IA R 1 MP1 BP ACC PCL TBLP TBLH TBHP STATUS SMOD LVD C IN T E G IN T C 0 IN T C 1 IN T C 2 M F I0 U nused M F I2 PA PAC PAPU PAW KUP PRM U nused W DTC TBC U nused U nused EEA EED
20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH
Bank 0 & Bank 1 ADRL ADRH ADCR0 ADCR1 ACERL CPC U nused U nused TM 0C0 TM 0C1 TM 0DL TM 0DH TM 0AL TM 0AH TM 1C0 TM 1C1 TM 1DL TM 1DH TM 1AL TM 1AH U nused U nused U nused U nused U nused U nused U nused U nused U nused U nused U nused U nused
HT66F03 Special Purpose Data Memory
Rev. 1.00
18
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH Bank 0 & Bank 1 IA R 0 MP0 IA R 1 MP1 BP ACC PCL TBLP TBLH TBHP STATUS SMOD LVD C IN T E G IN T C 0 IN T C 1 IN T C 2 M F I0 M F I1 M F I2 PA PAC PAPU PAW KUP PRM U nused W DTC TBC U nused U nused EEA EED 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH Bank 0 & Bank 1 ADRL ADRH ADCR0 ADCR1 ACERL CPC U nused U nused TM 0C0 TM 0C1 TM 0DL TM 0DH TM 0AL TM 0AH TM 1C0 TM 1C1 TM 1DL TM 1DH TM 1AL TM 1AH TM 2C0 TM 2C1 TM 2C2 TM 2DL TM 2DH TM 2AL TM 2AH TM 2BL TM 2BH U nused U nused U nused 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH Bank 0 & Bank 1 IA R 0 MP0 IA R 1 MP1 BP ACC PCL TBLP TBLH TBHP STATUS SMOD LVD C IN T E G IN T C 0 IN T C 1 IN T C 2 M F I0 U nused M F I2 PA PAC PAPU PAW KUP PRM U nused W DTC TBC U nused U nused EEA EED 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH Bank 0 Un Un Un Un Un C Un Un TM TM TM TM TM TM TM TM TM TM TM TM Un Un Un Un Un Un Un Un Un Un Un Un & Bank 1 used used used used used PC used used 0C0 0C1 0DL 0DH 0AL 0AH 1C0 1C1 1DL 1DH 1AL 1AH used used used used used used used used used used used used
HT66F04 Special Purpose Data Memory
HT68F03/HT68F04 Special Purpose Data Memory
H T 6 6 F 0 3 /H T 6 8 F 0 3 40H G e n e ra l P u rp o s e D a ta M e m o ry 7FH EEC 40H
H T 6 6 F 0 4 /H T 6 8 F 0 4 EEC G e n e ra l P u rp o s e D a ta M e m o ry 9FH
U nused
U nused
General Purpose Data Memory
Rev. 1.00
19
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
Special Function Register Description
Most of the Special Function Register details will be described in the relevant functional section, however several registers require a separate description in this section. Indirect Addressing Registers - IAR0, IAR1 The Indirect Addressing Registers, IAR0 and IAR1, although having their locations in normal RAM register space, do not actually physically exist as normal registers. The method of indirect addressing for RAM data manipulation uses these Indirect Addressing Registers and Memory Pointers, in contrast to direct memory addressing, where the actual memory address is specified. Actions on the IAR0 and IAR1 registers will result in no actual read or write operation to these registers but rather to the memory location specified by their corresponding Memory Pointers, MP0 or MP1. Acting as a pair, IAR0 and MP0 can together access data from Bank 0 while the IAR1 and MP1 register pair can access data from any bank. As the Indirect Addressing Registers are not physically implemented, reading the Indirect Addressing Registers indirectly will return a result of 00H and writing to the registers indirectly will result in no operation. Memory Pointers - MP0, MP1 Two Memory Pointers, known as MP0 and MP1 are provided. These Memory Pointers are physically implemented in the Data Memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data. When any operation to the relevant Indirect Addressing Registers is carried out, the actual address that the microcontroller is directed to, is the address specified by the related Memory Pointer. MP0, together with Indirect Addressing Register, IAR0, are used to access data from Bank 0, while MP1 and IAR1 are used to access data from all banks according to BP register. Direct Addressing can only be used with Bank 0, all other Banks must be addressed indirectly using MP1 and IAR1. Note that for this series of devices, the Memory Pointers, MP0 and MP1, are both 8-bit registers and used to access the Data Memory together with their corresponding indirect addressing registers IAR0 and IAR1. The following example shows how to clear a section of four Data Memory locations already defined as locations adres1 to adres4.
* Indirect Addressing Program Example
data .section data adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 code org 00h start: mov a,04h mov block,a mov a,offset adres1 mov mp0,a loop: clr inc sdz jmp IAR0 mp0 block loop ; setup size of block ; Accumulator loaded with first RAM address ; setup memory pointer with first RAM address ; clear the data at address defined by MP0 ; increment memory pointer ; check if last memory location has been cleared
continue: The important point to note here is that in the example shown above, no reference is made to specific RAM addresses.
Rev. 1.00
20
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
Bank Pointer - BP For this series of devices, the Data Memory is divided into two banks. Selecting the required Data Memory area is achieved using the Bank Pointer. Bit 0 is used to select Data Memory Banks 0~1. The Data Memory is initialised to Bank 0 after a reset, except for a WDT time-out reset in the Power Down Mode, in which case, the Data Memory bank remains unaffected. It should be noted that the Special Function Data Memory is not affected by the bank selection, which means that the Special Function Registers can be accessed from within any bank. Directly addressing the Data Memory will always result in Bank 0 being accessed irrespective of the value of the Bank Pointer. Accessing data from banks other than Bank 0 must be implemented using indirect addressing. Accumulator - ACC The Accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the ALU. The Accumulator is the place where all intermediate results from the ALU are stored. Without the Accumulator it would be necessary to write the result of each calculation or logical operation such as addition, subtraction, shift, etc., to the Data Memory resulting in higher programming and timing overheads. Data transfer operations usually involve the temporary storage function of the Accumulator; for example, when transferring data between one user defined register and another, it is necessary to do this by passing the data through the Accumulator as no direct transfer between two registers is permitted. Program Counter Low Register - PCL To provide additional program control functions, the low byte of the Program Counter is made accessible to programmers by locating it within the Special Purpose area of the Data Memory. By manipulating this register, direct jumps to other program locations are easily implemented. Loading a value directly into this PCL register will cause a jump to the specified Program Memory location, however, as the register is only 8-bit wide, only jumps within the current Program Memory page are permitted. When such operations are used, note that a dummy cycle will be inserted. Look-up Table Registers - TBLP, TBHP, TBLH These three special function registers are used to control operation of the look-up table which is stored in the Program Memory. TBLP and TBHP are the table pointer and indicates the location where the table data is located. Their value must be setup before any table read commands are executed. Their value can be changed, for example using the INC or DEC instructions, allowing for easy table data pointing and reading. TBLH is the location where the high order byte of the table data is stored after a table read data instruction has been executed. Note that the lower order table data byte is transferred to a user defined location.
* Bank Pointer Register
Bit Name R/W POR Bit 7 ~ 1 Bit 0
7 3/4 3/4 3/4
6 3/4 3/4 3/4
5 3/4 3/4 3/4
4 3/4 3/4 3/4
3 3/4 3/4 3/4
2 3/4 3/4 3/4
1 3/4 3/4 3/4
0 DMBP0 R/W 0
Unimplemented, read as 0 DMBP0: Select Data Memory Banks 0: Bank 0 1: Bank 1
Rev. 1.00
21
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
Status Register - STATUS This 8-bit register contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), and watchdog time-out flag (TO). These arithmetic/logical operation and system management flags are used to record the status and operation of the microcontroller. With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PDF flag. In addition, operations related to the status register may give different results due to the different instruction operations. The TO flag can be affected only by a system power-up, a WDT time-out or by executing the CLR WDT or HALT instruction. The PDF flag is affected only by executing the HALT or CLR WDT instruction or during a system power-up. The Z, OV, AC and C flags generally reflect the status of the latest operations.
* C is set if an operation results in a carry during an ad-
is also affected by a rotate through carry instruction.
* AC is set if an operation results in a carry out of the
low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared.
* Z is set if the result of an arithmetic or logical operation
is zero; otherwise Z is cleared.
* OV is set if an operation results in a carry into the high-
est-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared.
* PDF is cleared by a system power-up or executing the
CLR WDT instruction. PDF is set by executing the HALT instruction.
* TO is cleared by a system power-up or executing the
CLR WDT or HALT instruction. TO is set by a WDT time-out. In addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it.
dition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C
* STATUS Register
Bit Name R/W POR Bit 7, 6 Bit 5
7 3/4 3/4 3/4
6 3/4 3/4 3/4
5 TO R 0
4 PDF R 0
3 OV R/W x
2 Z R/W x
1 AC R/W x
0 C R/W x
x unknown
Bit 4
Bit 3
Bit 2
Bit 1
Unimplemented, read as 0 TO: Watchdog Time-Out flag 0: After power up or executing the CLR WDT or HALT instruction 1: A watchdog time-out occurred. PDF: Power down flag 0: After power up or executing the CLR WDT instruction 1: By executing the HALT instruction OV: Overflow flag 0: no overflow 1: an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa. Z: Zero flag 0: The result of an arithmetic or logical operation is not zero 1: The result of an arithmetic or logical operation is zero AC: Auxiliary flag 0: no auxiliary carry 1: an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction C: Carry flag 0: no carry-out 1: an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation C is also affected by a rotate through carry instruction.
Bit 0
Rev. 1.00
22
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
EEPROM Data Memory
The device contains an area of internal EEPROM Data Memory. EEPROM, which stands for Electrically Erasable Programmable Read Only Memory, is by its nature a non-volatile form of re-programmable memory, with data retention even when its power supply is removed. By incorporating this kind of data memory, a whole new host of application possibilities are made available to the designer. The availability of EEPROM storage allows information such as product identification numbers, calibration values, specific user data, system setup data or other product information to be stored directly within the product microcontroller. The process of reading and writing data to the EEPROM memory has been reduced to a very trivial affair. EEPROM Data Memory Structure The EEPROM Data Memory capacity is 648 bits for this series of devices. Unlike the Program Memory and RAM Data Memory, the EEPROM Data Memory is not directly mapped into memory space and is therefore not directly addressable in the same way as the other types of memory. Read and Write operations to the EEPROM are carried out in single byte operations using an address and data register in Bank 0 and a single control register in Bank 1. Device All devices EEPROM Registers Three registers control the overall operation of the internal EEPROM Data Memory. These are the address register, EEA, the data register, EED and a single control register, EEC. As both the EEA and EED registers are located in Bank 0, they can be directly accessed in the same was as any other Special Function Register. The EEC register however, being located in Bank1, cannot be addressed directly and can only be read from or written to indirectly using the MP1 Memory Pointer and Indirect Addressing Register, IAR1. Because the EEC control register is located at address 40H in Bank 1, the MP1 Memory Pointer must first be set to the value 40H and the Bank Pointer register, BP, set to the value, 01H, before any operations on the EEC register are executed. Capacity 648 Address 00H ~ 3FH
* EEPROM Register List
Name EEA EED EEC
* EEA Register
Bit 7 3/4 D7 3/4 6 3/4 D6 3/4 5 D5 D5 3/4 4 D4 D4 3/4 3 D3 D3 WREN 2 D2 D2 WR 1 D1 D1 RDEN 0 D0 D0 RD
Bit Name R/W POR Bit 7 ~ 6 Bit 5 ~ 0
7 3/4 3/4 3/4
6 3/4 3/4 3/4
5 D5 R/W x
4 D4 R/W x
3 D3 R/W x
2 D2 R/W x
1 D1 R/W x
0 D0 R/W x
x unknown
Unimplemented, read as 0 Data EEPROM address Data EEPROM address bit 5 ~ bit 0
Rev. 1.00
23
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
* EEC Register
Bit Name R/W POR Bit 7 ~ 4 Bit 3
7 3/4 3/4 3/4
6 3/4 3/4 3/4
5 3/4 3/4 3/4
4 3/4 3/4 3/4
3 WREN R/W 0
2 WR R/W 0
1 RDEN R/W 0
0 RD R/W 0
Unimplemented, read as 0 WREN: Data EEPROM Write Enable 0: Disable 1: Enable This is the Data EEPROM Write Enable Bit which must be set high before Data EEPROM write operations are carried out. Clearing this bit to zero will inhibit Data EEPROM write operations.
Bit 2
WR: EEPROM Write Control 0: Write cycle has finished 1: Activate a write cycle This is the Data EEPROM Write Control Bit and when set high by the application program will activate a write cycle. This bit will be automatically reset to zero by the hardware after the write cycle has finished. Setting this bit high will have no effect if the WREN has not first been set high.
Bit 1
RDEN: Data EEPROM Read Enable 0: Disable 1: Enable This is the Data EEPROM Read Enable Bit which must be set high before Data EEPROM read operations are carried out. Clearing this bit to zero will inhibit Data EEPROM read operations.
Bit 0
RD: EEPROM Read Control 0: Read cycle has finished 1: Activate a read cycle This is the Data EEPROM Read Control Bit and when set high by the application program will activate a read cycle. This bit will be automatically reset to zero by the hardware after the read cycle has finished. Setting this bit high will have no effect if the RDEN has not first been set high.
Note: The WREN, WR, RDEN and RD can not be set to 1 at the same time in one instruction. The WR and RD can not be set to 1 at the same time.
* EED Register
Bit Name R/W POR Bit 7 ~ 0
7 D7 R/W x
6 D6 R/W x
5 D5 R/W x
4 D4 R/W x
3 D3 R/W x
2 D2 R/W x
1 D1 R/W x
0 D0 R/W x
x unknown
Data EEPROM address Data EEPROM address bit 7 ~ bit 0
Rev. 1.00
24
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
Reading Data from the EEPROM To read data from the EEPROM, the read enable bit, RDEN, in the EEC register must first be set high to enable the read function. The EEPROM address of the data to be read must then be placed in the EEA register. If the RD bit in the EEC register is now set high, a read cycle will be initiated. Setting the RD bit high will not initiate a read operation if the RDEN bit has not been set. When the read cycle terminates, the RD bit will be automatically cleared to zero, after which the data can be read from the EED register. The data will remain in the EED register until another read or write operation is executed. The application program can poll the RD bit to determine when the data is valid for reading. Writing Data to the EEPROM To write data to the EEPROM, the write enable bit, WREN, in the EEC register must first be set high to enable the write function. The EEPROM address of the data to be written must then be placed in the EEA register and the data placed in the EED register. If the WR bit in the EEC register is now set high, an internal write cycle will then be initiated. Setting the WR bit high will not initiate a write cycle if the WREN bit has not been set. As the EEPROM write cycle is controlled using an internal t im e r w h o s e o p e r at i o n i s a s y n c hr o n o u s t o microcontroller system clock, a certain time will elapse before the data will have been written into the EEPROM. Detecting when the write cycle has finished can be implemented either by polling the WR bit in the EEC register or by using the EEPROM interrupt. When the write cycle terminates, the WR bit will be automatically cleared to zero by the microcontroller, informing the user that the data has been written to the EEPROM. The application program can therefore poll the WR bit to determine when the write cycle has ended. Write Protection Protection against inadvertent write operation is provided in several ways. After the device is powered-on the Write Enable bit in the control register will be cleared preventing any write operations. Also at power-on the Bank Pointer, BP, will be reset to zero, which means that Data Memory Bank 0 will be selected. As the EEPROM control register is located in Bank 1, this adds a further measure of protection against spurious write operations. During normal program operation, ensuring that the Write Enable bit in the control register is cleared will safeguard against incorrect write operations. EEPROM Interrupt The EEPROM write or read interrupt is generated when an EEPROM write or read cycle has ended. The EEPROM interrupt must first be enabled by setting the DEE bit in the relevant interrupt register. However as the EEPROM is contained within a Multi-function Interrupt, the associated multi-function interrupt enable bit must also be set. When an EEPROM write cycle ends, the DEF request flag and its associated multi-function interrupt request flag will both be set. If the global, EEPROM and Multi-function interrupts are enabled and the stack is not full, a jump to the associated Multi-function Interrupt vector will take place. When the interrupt is serviced only the Multi-function interrupt flag will be automatically reset, the EEPROM interrupt flag must be manually reset by the application program. More details can be obtained in the Interrupt section. Programming Considerations Care must be taken that data is not inadvertently written to the EEPROM. Protection can be enhanced by ensuring that the Write Enable bit is normally cleared to zero when not writing. Also the Bank Pointer could be normally cleared to zero as this would inhibit access to Bank 1 where the EEPROM control register exist. Although certainly not necessary, consideration might be given in the application program to the checking of the validity of new write data by a simple read back process.
Rev. 1.00
25
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
* Programming Examples
Reading data from the EEPROM - polling method MOV A, EEPROM_ADRES MOV EEA, A MOV A, 040H MOV MP1, A MOV A, 01H MOV BP, A SET IAR1.1 SET IAR1.0 BACK: SZ IAR1.0 JMP BACK CLR IAR1 CLR BP MOV A, EEDATA MOV READ_DATA, A ; user defined address ; setup memory pointer MP1 ; MP1 points to EEC register ; setup Bank Pointer ; set RDEN bit, enable read operations ; start Read Cycle - set RD bit ; check for read cycle end ; disable EEPROM read/write ; move read data to register
Writing Data to the EEPROM - polling method MOV A, EEPROM_ADRES ; user defined address MOV EEA, A MOV A, EEPROM_DATA ; user defined data MOV EED, A MOV A, 040H ; setup memory pointer MP1 MOV MP1, A ; MP1 points to EEC register MOV A, 01H ; setup Bank Pointer MOV BP, A SET IAR1.3 ; set WREN bit, enable write operations SET IAR1.2 ; start Write Cycle - set WR bit BACK: SZ IAR1.2 ; check for write cycle end JMP BACK CLR IAR1 ; disable EEPROM read/write CLR BP
Rev. 1.00
26
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
Oscillator
Various oscillator options offer the user a wide range of functions according to their various application requirements. The flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. Oscillator selections and operation are selected through a combination of configuration options and registers. Oscillator Overview In addition to being the source of the main system clock the oscillators also provide clock sources for the Watchdog Timer and Time Base Interrupts. External oscillators requiring some external components as well as fully integrated internal oscillators, requiring no external components, are provided to form a wide range of both fast and slow system oscillators. All oscillator options are selected through the configuration options. The higher frequency oscillators provide higher performance but carry with it the disadvantage of higher power requirements, while the opposite is of course true for the lower frequency oscillators. With the capability of dynamically switching between fast and slow system clock, the device has the flexibility to optimize the performance/power ratio, a feature especially important in power sensitive portable applications. Type External Crystal External RC Internal High Speed RC External Low Speed Crystal Internal Low Speed RC Name HXT ERC HIRC LXT LIRC Freq. 400kHz~ 20MHz 8MHz 4, 8 or 12MHz 32.768kHz 32kHz Pins OSC1/ OSC2 OSC1 3/4 XT1/ XT2 3/4
Oscillator Types System Clock Configurations There are five methods of generating the system clock, three high speed oscillators and two low speed oscillators. The high speed oscillators are the external crystal/ ceramic oscillator, external RC network oscillator and the internal 4MHz, 8MHz or 12MHz RC oscillator. The two low speed oscillators are the internal 32kHz RC oscillator and the external 32.768kHz crystal oscillator. Selecting whether the low or high speed oscillator is used as the system oscillator is implemented using the HLCLK bit and CKS2 ~ CKS0 bits in the SMOD register and as the system clock can be dynamically selected.
High Speed Oscillation HXT ERC HIRC High Speed Oscillation Configuration Option Low Speed Oscillation LIRC
fH
6-stage Prescaler
fH/2 fH/4 fH/8 fH/16 fH/32 fH/64 fL
LXT Low Speed Oscillation Configuration Option HLCLK, CKS2~CKS0 bits
fSYS
fSUB
Fast Wake-up from SLEEP Mode or IDLE Mode Control (for HXT only)
System Clock Configurations
Rev. 1.00
27
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
The actual source clock used for each of the high speed and low speed oscillators is chosen via configuration options. The frequency of the slow speed or high speed system clock is also determined using the HLCLK bit and CKS2 ~ CKS0 bits in the SMOD register. Note that two oscillator selections must be made namely one high speed and one low speed system oscillators. It is not possible to choose a no-oscillator selection for either the high or low speed oscillator. The OSC1 and OSC2 pins are used to connect the external components for the external crystal, external RC and external low speed crystal oscillators. Once the OSC1 or both OSC1 and OSC2 pins are used for ERC, HXT or LXT oscillators, the corresponding low speed oscillator must be the Internal Low speed RC oscillator LIRC. Therefore there are some limitations to select the high speed and low speed oscillators for the high and low speed system clock sources. The available selections for high speed and low speed oscillators are shown in the following table. Available Oscillator Selections 1 High Speed Oscillator Low Speed Oscillator HXT LIRC 2 ERC LIRC 3 4 Crystal Oscillator C1 and C2 Values Crystal Frequency 12MHz 8MHz 4MHz 1MHz Note: C1 0pF 0pF 0pF 100pF C2 0pF 0pF 0pF 100pF
C1 and C2 values are for guidance only.
Crystal Recommended Capacitor Values External RC Oscillator - ERC Using the ERC oscillator only requires that a resistor, with a value between 56kW and 2.4MW, is connected between OSC1 and VDD, and a capacitor is connected between OSC1 and ground, providing a low cost oscillator configuration. It is only the external resistor that determines the oscillation frequency; the external capacitor has no influence over the frequency and is connected for stability purposes only. Device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. As a resistance/frequency reference point, it can be noted that with an external 120kW resistor connected and with a 5V voltage power supply and temperature of 25C degrees, the oscillator will have a frequency of 8MHz within a tolerance of 3%. Here only the OSC1 pin is used, which is shared with I/O pin PA6, leaving pin PA5 free for use as a normal I/O pin.
V
DD
Oscillator Types
HIRC HIRC LIRC LXT
External Crystal/ Ceramic Oscillator - HXT The External Crystal/ Ceramic System Oscillator is one of the high frequency oscillator choices, which is selected via configuration option. For most crystal oscillator configurations, the simple connection of a crystal across OSC1 and OSC2 will create the necessary phase shift and feedback for oscillation, without requiring external capacitors. However, for some crystal types and frequencies, to ensure oscillation, it may be necessary to add two small value capacitors, C1 and C2. Using a ceramic resonator will usually require two small value capacitors, C1 and C2, to be connected as shown for oscillation to occur. The values of C1 and C2 should be selected in consultation with the crystal or resonator manufacturers specification.
C1 Rp OSC1 Rf In te r n a l O s c illa to r C ir c u it
R
OSC
OSC1 470pF
External RC Oscillator - ERC Internal RC Oscillator - HIRC The internal RC oscillator is a fully integrated system oscillator requiring no external components. The internal RC oscillator has three fixed frequencies of either 4MHz, 8MHz or 12MHz. Device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. As a result, at a power supply of either 3V or 5V and at a temperature of 25C degrees, the fixed oscillation frequency of the internal 32kHz oscillator will have a tolerance within 10%. Note that if this internal
C2
OSC2
T o in te r n a l c ir c u its
N o te : 1 . R p is n o r m a lly n o t r e q u ir e d . C 1 a n d C 2 a r e r e q u ir e d . 2 . A lth o u g h n o t s h o w n O S C 1 /O S C 2 p in s h a v e a p a r a s itic c a p a c ita n c e o f a r o u n d 7 p F .
Crystal/Resonator Oscillator - HXT
Rev. 1.00
28
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
system clock option is selected, as it requires no external pins for its operation, I/O pins PA6 and PA5 are free for use as normal I/O pins or external 32.768 kHz crystal oscillator (LXT) pins. External 32.768kHz Crystal Oscillator - LXT The External 32.768kHz Crystal System Oscillator is one of the low frequency oscillator choices, which is selected via configuration option. This clock source has a fixed frequency of 32.768kHz and requires a 32.768kHz crystal to be connected between pins OSC1 and OSC2. The external resistor and capacitor components connected to the 32.768kHz crystal are necessary to provide oscillation. For applications where precise frequencies are essential, these components may be required to provide frequency compensation due to different crystal manufacturing tolerances. During power-up there is a time delay associated with the LXT oscillator waiting for it to start-up. When the microcontroller enters the SLEEP or IDLE Mode, the system clock is switched off to stop microcontroller activity and to conserve power. However, in many microcontroller applications it may be necessary to keep the internal timers operational even when the microcontroller is in the SLEEP or IDLE Mode. To do this, another clock, independent of the system clock, must be provided. However, for some crystals, to ensure oscillation and accurate frequency generation, it is necessary to add two small value external capacitors, C1 and C2. The exact values of C1 and C2 should be selected in consultation with the crystal or resonator manufacturers specification. The external parallel feedback resistor, Rp, is required. Some configuration options determine if the OSC1 and OSC2 pins are used for the LXT oscillator or as I/O pins.
* If the LXT oscillator is not used for any clock source,
LXT Oscillator C1 and C2 Values Crystal Frequency 32.768kHz Note: C1 10pF C2 10pF
1. C1 and C2 values are for guidance only. 2. RP=5M~10MW is recommended.
32.768kHz Crystal Recommended Capacitor Values LXT Oscillator Low Power Function The LXT oscillator can function in one of two modes, the Quick Start Mode and the Low Power Mode. The mode selection is executed using the LXTLP bit in the TBC register. LXTLP Bit 0 1 LXT Mode Quick Start Low-power
After power on the LXTLP bit will be automatically cleared to zero ensuring that the LXT oscillator is in the Quick Start operating mode. In the Quick Start Mode the LXT oscillator will power up and stabilise quickly. However, after the LXT oscillator has fully powered up it can be placed into the Low-power mode by setting the LXTLP bit high. The oscillator will continue to run but with reduced current consumption, as the higher current consumption is only required during the LXT oscillator start-up. In power sensitive applications, such as battery applications, where power consumption must be kept to a minimum, it is therefore recommended that the application program sets the LXTLP bit high about 2 seconds after power-on. It should be noted that, no matter what condition the LXTLP bit is set to, the LXT oscillator will always function normally, the only difference is that it will take more time to start up if in the Low-power mode. Internal 32kHz Oscillator - LIRC The Internal 32kHz System Oscillator is one of the low frequency oscillator choices, which is selected via configuration option. It is a fully integrated RC oscillator with a typical frequency of 32kHz at 5V, requiring no external components for its implementation. Device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. As a result, at a power supply of 5V and at a temperature of 25C degrees, the fixed oscillation frequency of 32kHz will have a tolerance within 10%.
the OSC1 and OSC2 pins can be used as normal I/O pins.
* If the LXT oscillator is used for any clock source, the
32.768kHz crystal should be connected to the OSC1 and OSC2 pins.
C1 Rp 3 2 .7 6 8 kH z OSC2 C2 T o in te r n a l c ir c u its OSC1 In te r n a l O s c illa to r C ir c u it
N o te : 1 . R p , C 1 a n d C 2 a r e r e q u ir e d . 2 . A lth o u g h n o t s h o w n p in s h a v e a p a r a s itic c a p a c ita n c e o f a r o u n d 7 p F .
External LXT Oscillator
Rev. 1.00
29
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
Operating Modes and System Clocks
P re s e n t d a y appl i c a t i ons r equi r e t ha t t h e i r microcontrollers have high performance but often still demand that they consume as little power as possible, conflicting requirements that are especially true in battery powered portable applications. The fast clocks required for high performance will by their nature increase current consumption and of course vice-versa, lower speed clocks reduce current consumption. As Holtek has provided these devices with both high and low speed clock sources and the means to switch between them dynamically, the user can optimise the operation of their microcontroller to achieve the best performance/power ratio. System Clocks The device has many different clock sources for both the CPU and peripheral function operation. By providing the user with a wide range of clock options using configuration options and register programming, a clock system can be configured to obtain maximum application performance.
High Speed Oscillation HXT ERC HIRC High Speed Oscillation Configuration Option Low Speed Oscillation LIRC
The main system clock, can come from either a high frequency, fH, or low frequency, fL, source, and is selected using the HLCLK bit and CKS2~CKS0 bits in the SMOD register. The high speed system clock can be sourced from either an HXT, ERC or HIRC oscillator, selected via a configuration option. The low speed system clock source can be sourced from internal clock fL. If fL is selected then it can be sourced by either the LXT or LIRC oscillators, selected via a configuration option. The other choice, which is a divided version of the high speed system oscillator has a range of fH/2~fH/64. There are two additional internal clocks for the peripheral circuits, the substitute clock, fSUB, and the Time Base clock, fTBC. Each of these internal clocks are sourced by either the LXT or LIRC oscillators, selected via configuration options. The fSUB clock is used to provide a substitute clock for the microcontroller just after a wake-up has occurred to enable faster wake-up times.
fH
6-stage Prescaler
fH/2 fH/4 fH/8 fH/16 fH/32 fH/64 fL
LXT Low Speed Oscillation Configuration Option HLCLK, CKS2~CKS0 bits
fSYS
fSUB
Fast Wake-up from SLEEP Mode or IDLE Mode Control (for HXT only)
fTBC fTB fSYS/4
TBCK Time Base
fSUB fS fSYS/4
Configuration Option WDT
System Clock Configurations Note: When the system clock source fSYS is switched to fL from fH, the high speed oscillation will stop to conserve the power. Thus there is no fH~fH/64 for peripheral circuit to use. 30 April 16, 2010
Rev. 1.00
HT66F03/HT66F04/HT68F03/HT68F04
Together with fSYS/4 it is also used as one of the clock sources for the Watchdog timer. The fTBC clock is used as a source for the Time Base interrupt functions and for the TMs. System Operation Modes There are six different modes of operation for the microcontroller, each one with its own special characteristics and which can be chosen according to the specific performance and power requirements of the application. There are two modes allowing normal operation of the microcontroller, the NORMAL Mode and SLOW Mode. The remaining four modes, the SLEEP0, SLEEP1, IDLE0 and IDLE1 Mode are used when the microcontroller CPU is switched off to conserve power.
Description Operation Mode CPU NORMAL Mode SLOW Mode IDLE0 Mode IDLE1 Mode SLEEP0 Mode SLEEP1 Mode On On Off Off Off Off fSYS fH~ fH/64 fL Off On Off Off fSUB On On On On Off On fS On On On/Off On Off On fTBC On On On On Off Off
* NORMAL Mode
As the name suggests this is one of the main operating modes where the microcontroller has all of its functions operational and where the system clock is provided by one of the high speed oscillators. This mode operates allowing the microcontroller to operate normally with a clock source will come from one of the high speed oscillators, either the HXT, ERC or HIRC oscillators. The high speed oscillator will however first be divided by a ratio ranging from 1 to 64, the actual ratio being selected by the CKS2~LCKS0 and HLCLK bits in the SMOD register. Although a high speed oscillator is used, running the microcontroller at a divided clock ratio reduces the operating current.
* SLOW Mode
to operate if the LVDEN is 1 or the Watchdog Timer function is enabled and if its clock source is chosen via configuration option to come from the fSUB.
* IDLE0 Mode
This is also a mode where the microcontroller operates normally although now with a slower speed clock source. The clock source used will be from one of the low speed oscillators, either the LXT or the LIRC. Running the microcontroller in this mode allows it to run with much lower operating currents. In the SLOW Mode, the fH is off.
* SLEEP0 Mode
The IDLE0 Mode is entered when a HALT instruction is executed and when the IDLEN bit in the SMOD register is high and the FSYSON bit in the WDTC register is low. In the IDLE0 Mode the system oscillator will be inhibited from driving the CPU but some peripheral functions will remain operational such as the Watchdog Timer, TMs and SIM. In the IDLE0 Mode, the system oscillator will be stopped. In the IDLE0 Mode the Watchdog Timer clock, fS, will either be on or off depending upon the fS clock source. If the source is fSYS/4 then the fS clock will be off, and if the source comes from fSUB then fS will be on.
* IDLE1 Mode
The SLEEP Mode is entered when an HALT instruction is executed and when the IDLEN bit in the SMOD register is low. In the SLEEP0 mode the CPU will be stopped, and the fSUB and fS clocks will be stopped too, and the Watchdog Timer function is disabled. In this mode, the LVDEN is must set to 0. If the LVDEN is set to 1, it wont enter the SLEEP0 Mode.
* SLEEP1 Mode
The IDLE1 Mode is entered when an HALT instruction is executed and when the IDLEN bit in the SMOD register is high and the FSYSON bit in the WDTC register is high. In the IDLE1 Mode the system oscillator will be inhibited from driving the CPU but may continue to provide a clock source to keep some peripheral functions operational such as the Watchdog Timer, TMs and SIM. In the IDLE1 Mode, the system oscillator will continue to run, and this system oscillator may be high speed or low speed system oscillator. In the IDLE1 Mode the Watchdog Timer clock, fS, will be on. If the source is fSYS/4 then the fS clock will be on, and if the source comes from fSUB then fS will be on.
The SLEEP Mode is entered when an HALT instruction is executed and when the IDLEN bit in the SMOD register is low. In the SLEEP1 mode the CPU will be stopped. However the fSUB and fS clocks will continue
Rev. 1.00
31
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
Control Register A single register, SMOD, is used for overall control of the internal clocks within the device.
* SMOD Register
Bit Name R/W POR Bit 7~5
7 CKS2 R/W 0
6 CKS1 R/W 0
5 CKS0 R/W 0
4 FSTEN R/W 0
3 LTO R 0
2 HTO R 0
1 IDLEN R/W 1
0 HLCLK R/W 1
CKS2~CKS0: The system clock selection when HLCLK is 0 000: fL (fLXT or fLIRC) 001: fL (fLXT or fLIRC) 010: fH/64 011: fH/32 100: fH/16 101: fH/8 110: fH/4 111: fH/2 These three bits are used to select which clock is used as the system clock source. In addition to the system clock source, which can be either the LXT or LIRC, a divided version of the high speed system oscillator can also be chosen as the system clock source. FSTEN: Fast Wake-up Control (only for HXT) 0: Disable 1: Enable This is the Fast Wake-up Control bit which determines if the fSUB clock source is initially used after the device wakes up. When the bit is high, the fSUB clock source can be used as a temporary system clock to provide a faster wake up time as the fSUB clock is available. LTO: Low speed system oscillator ready flag 0: Not ready 1: Ready This is the low speed system oscillator ready flag which indicates when the low speed system oscillator is stable after power on reset or a wake-up has occurred. The flag will be low when in the SLEEP0 Mode but after a wake-up has occurred, the flag will change to a high level after 1024 clock cycles if the LXT oscillator is used and 1~2 clock cycles if the LIRC oscillator is used. HTO: High speed system oscillator ready flag 0: Not ready 1: Ready This is the high speed system oscillator ready flag which indicates when the high speed system oscillator is stable. This flag is cleared to 0 by hardware when the device is powered on and then changes to a high level after the high speed system oscillator is stable. Therefore this flag will always be read as 1 by the application program after device power-on. The flag will be low when in the SLEEP or IDLE0 Mode but after a wake-up has occurred, the flag will change to a high level after 1024 clock cycles if the HXT oscillator is used and after 15~16 clock cycles if the ERC or HIRC oscillator is used. IDLEN: IDLE Mode control 0: Disable 1: Enable This is the IDLE Mode Control bit and determines what happens when the HALT instruction is executed. If this bit is high, when a HALT instruction is executed the device will enter the IDLE Mode. In the IDLE1 Mode the CPU will stop running but the system clock will continue to keep the peripheral functions operational, if FSYSON bit is high. If FSYSON bit is low, the CPU and the system clock will all stop in IDLE0 mode. If the bit is low the device will enter the SLEEP Mode when a HALT instruction is executed. HLCLK: system clock selection 0: fH/2 ~ fH/64 or fL 1: fH This bit is used to select if the fH clock or the fH/2 ~ fH/64 or fL clock is used as the system clock. When the bit is high the fH clock will be selected and if low the fH/2 ~ fH/64 or fL clock will be selected. When system clock switches from the fH clock to the fL clock and the fH clock will be automatically switched off to conserve power. 32 April 16, 2010
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Rev. 1.00
HT66F03/HT66F04/HT68F03/HT68F04
Fast Wake-up To minimise power consumption the device can enter the SLEEP or IDLE0 Mode, where the system clock source to the device will be stopped. However when the device is woken up again, it can take a considerable time for the original system oscillator to restart, stabilise and allow normal operation to resume. To ensure the device is up and running as fast as possible a Fast Wake-up function is provided, which allows fSUB, namely either the LXT or LIRC oscillator, to act as a temporary clock to first drive the system until the original system oscillator has stabilised. As the clock source for the Fast Wake-up function is fSUB, the Fast Wake-up function is only available in the SLEEP1 and IDLE0 modes. When the device is woken up from the SLEEP0 mode, the Fast Wake-up function has no effect because the fSUB clock is stopped. The Fast Wake-up enable/disable function is controlled using the FSTEN bit in the SMOD register. If the HXT oscillator is selected as the NORMAL Mode system clock, and if the Fast Wake-up function is enabled, then it will take one to two tSUB clock cycles of the LIRC oscillator for the system to wake-up. The system will then initially run under the fSUB clock source until 1024 HXT clock cycles have elapsed, at which point the HTO flag will switch high and the system will switch over to operating from the HXT oscillator. If the ERC or HIRC oscillators or LIRC oscillator is used as the system oscillator then it will take 15~16 clock cycles of the ERC or HIRC or 1~2 cycles of the LIRC to wake up the system from the SLEEP or IDLE0 Mode. The Fast Wake-up bit, FSTEN will have no effect in these cases.
System Oscillator
FSTEN Bit 0
Wake-up Time (SLEEP0 Mode) 1024 HXT cycles 1024 HXT cycles 15~16 ERC cycles 15~16 HIRC cycles 1~2 LIRC cycles 1024 LTX cycles
Wake-up Time (SLEEP1 Mode)
Wake-up Time (IDLE0 Mode)
Wake-up Time (IDLE1 Mode) 1~2 HXT cycles 1~2 HXT cycles 1~2 ERC cycles 1~2 HIRC cycles 1~2 LIRC cycles 1~2 LXT cycles
1024 HXT cycles 1~2 fSUB cycles (System runs with fSUB first for 1024 HXT cycles and then switches over to run with the HXT clock) 15~16 ERC cycles 15~16 HIRC cycles 1~2 LIRC cycles 1024 LXT cycles Wake-Up Times
HXT
1 X X X X
ERC HIRC LIRC LXT
Note that if the Watchdog Timer is disabled, which means that the LXT and LIRC are all both off, then there will be no Fast Wake-up function available when the device wakes-up from the SLEEP0 Mode.
fS
NORMAL Y S = fH ~ fH /6 4 fH o n C P U ru n fS Y S o n fT B C o n fS U B o n
ID L E 1 H A L T in s tr u c tio n is e x e c u te d C P U s to p ID L E N = 1 FSYSO N=1 fS Y S o n fT B C o n fS U B o n
SLEEP0 H A L T in s tr u c tio n is e x e c u te d fS Y S o ff C P U s to p ID L E N = 0 fT B C o ff fS U B o ff W D T & L V D o ff
ID L E 0 H A L T in s tr u c tio n is e x e c u te d C P U s to p ID L E N = 1 FSYSO N=0 fS Y S o ff fT B C o n fS U B o n
SLEEP1 H A L T in s tr u c tio n is e x e c u te d fS Y S o ff C P U s to p ID L E N = 0 fT B C o ff fS U B o n W D T orLVD on
SLOW fS Y S = fL fL o n C P U ru n fS Y S o n fT B C o n fS U B o n fH o ff
Rev. 1.00
33
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
Operating Mode Switching and Wake-up The device can switch between operating modes dynamically allowing the user to select the best performance/power ratio for the present task in hand. In this way microcontroller operations that do not require high performance can be executed using slower clocks thus requiring less operating current and prolonging battery life in portable applications. In simple terms, Mode Switching between the NORMAL Mode and SLOW Mode is executed using the HLCLK bit and CKS2~CKS0 bits in the SMOD register while Mode Switching from the NORMAL/SLOW Modes to the SLEEP/IDLE Modes is executed via the HALT instruction. When a HALT instruction is executed, whether the device enters the IDLE Mode or the SLEEP Mode is determined by the condition of the IDLEN bit in the SMOD register and FSYSON in the WDTC register. When the HLCLK bit switches to a low level, which implies that clock source is switched from the high speed clock source, fH, to the clock source, fH/2~fH/64 or fL. If the clock is from the fL, the high speed clock source will stop running to conserve power. When this happens it must be noted that the fH/16 and fH/64 internal clock sources will also stop running, which may affect the operation of other internal functions such as the TMs and the SIM. The accompanying flowchart shows what happens when the device moves between the various operating modes. NORMAL Mode to SLOW Mode Switching When running in the NORMAL Mode, which uses the high speed system oscillator, and therefore consumes more power, the system clock can switch to run in the SLOW Mode by set the HLCLK bit to 0 and set the CKS2~CKS0 bits to 000 or 001 in the SMOD register. This will then use the low speed system oscillator which will consume less power. Users may decide to do this for certain operations which do not require high performance and can subsequently reduce power consumption. The SLOW Mode is sourced from the LXT or the LIRC oscillators and therefore requires these oscillators to be stable before full mode switching occurs. This is monitored using the LTO bit in the SMOD register.
NO RM AL M ode
C K S 2 ~ C K S 0 = 00xB & HLCLK = 0 SLO W M ode
W D T a n d L V D a r e a ll o ff ID L E N = 0 H A L T in s tr u c tio n is e x e c u te d SLEEP0 M ode
W D T o r L V D is o n ID L E N = 0 H A L T in s tr u c tio n is e x e c u te d SLEEP1 M ode
ID L E N = 1 , F S Y S O N = 0 H A L T in s tr u c tio n is e x e c u te d
ID E L 0 M o d e ID L E N = 1 , F S Y S O N = 1 H A L T in s tr u c tio n is e x e c u te d ID L E 1 M o d e
Rev. 1.00
34
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
SLO W
M ode
C KS2~C KS0000B,001B as H LC LK=0 orH LCLK=1 NO RM AL M ode W D T a n d L V D a r e a ll o ff ID L E N = 0 H A L T in s tr u c tio n is e x e c u te d SLEEP0 M ode
W D T o r L V D is o n ID L E N = 0 H A L T in s tr u c tio n is e x e c u te d SLEEP1 M ode
ID L E N = 1 , F S Y S O N = 0 H A L T in s tr u c tio n is e x e c u te d
ID L E 0 M o d e ID L E N = 1 , F S Y S O N = 1 H A L T in s tr u c tio n is e x e c u te d ID L E 1 M o d e
SLOW Mode to NORMAL Mode Switching In SLOW Mode the system uses either the LXT or LIRC low speed system oscillator. To switch back to the NORMAL Mode, where the high speed system oscillator is used, the HLCLK bit should be set to 1 or HLCLK bit is 0, but CKS2~CKS0 is set to 010, 011, 100, 101, 110 or 111. As a certain amount of time will be required for the high frequency clock to stabilise, the status of the HTO bit is checked. The amount of time required for high speed system oscillator stabilization depends upon which high speed system oscillator type is used.
Entering the SLEEP0 Mode There is only one way for the device to enter the SLEEP0 Mode and that is to execute the HALT instruction in the application program with the IDLEN bit in SMOD register equal to 0 and the WDT and LVD both off. When this instruction is executed under the conditions described above, the following will occur:
* The system clock, WDT clock and Time Base clock
will be stopped and the application program will stop at the HALT instruction.
* The Data Memory contents and registers will maintain
their present condition.
* The WDT will be cleared and stopped no matter if the
WDT clock source originates from the fSUB clock or from the system clock.
* The I/O ports will maintain their present conditions. * In the status register, the Power Down flag, PDF, will
be set and the Watchdog time-out flag, TO, will be cleared.
Rev. 1.00
35
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
Entering the SLEEP1 Mode There is only one way for the device to enter the SLEEP1 Mode and that is to execute the HALT instruction in the application program with the IDLEN bit in SMOD register equal to 0 and the WDT or LVD on. When this instruction is executed under the conditions described above, the following will occur:
* The system clock and Time Base clock will be
Entering the IDLE1 Mode There is only one way for the device to enter the IDLE1 Mode and that is to execute the HALT instruction in the application program with the IDLEN bit in SMOD register equal to 1 and the FSYSON bit in WDTC register equal to 1. When this instruction is executed under the with conditions described above, the following will occur:
* The system clock and Time Base clock and fSUB clock
stopped and the application program will stop at the HALT instruction, but the WDT or LVD will remain with the clock source coming from the fSUB clock.
* The Data Memory contents and registers will maintain
will be on and the application program will stop at the HALT instruction.
* The Data Memory contents and registers will maintain
their present condition.
* The WDT will be cleared and resume counting if the
their present condition.
* The WDT will be cleared and resume counting if the
WDT clock source is selected to come from the fSUB clock as the WDT is enabled.
* The I/O ports will maintain their present conditions. * In the status register, the Power Down flag, PDF, will
WDT is enabled regardless of the WDT clock source which originates from the fSUB clock or from the system clock.
* The I/O ports will maintain their present conditions. * In the status register, the Power Down flag, PDF, will
be set and the Watchdog time-out flag, TO, will be cleared. Entering the IDLE0 Mode There is only one way for the device to enter the IDLE0 Mode and that is to execute the HALT instruction in the application program with the IDLEN bit in SMOD register equal to 1 and the FSYSON bit in WDTC register equal to 0. When this instruction is executed under the conditions described above, the following will occur:
* The system clock will be stopped and the application
be set and the Watchdog time-out flag, TO, will be cleared. Standby Current Considerations As the main reason for entering the SLEEP or IDLE Mode is to keep the current consumption of the device to as low a value as possible, perhaps only in the order of several micro-amps except in the IDLE1 Mode, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimised. Special attention must be made to the I/O pins on the device. All high-impedance input pins must be connected to either a fixed high or low level as any floating input pins could create internal oscillations and result in increased current consumption. This also applies to devices which have different package types, as there may be unbonbed pins. These must either be setup as outputs or if setup as inputs must have pull-high resistors connected. Care must also be taken with the loads, which are connected to I/O pins, which are setup as outputs. These should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other CMOS inputs. Also note that additional standby current will also be required if the configuration options have enabled the LXT or LIRC oscillator. In the IDLE1 Mode the system oscillator is on, if the system oscillator is from the high speed system oscillator, the additional standby current will also be perhaps in the order of several hundred micro-amps
program will stop at the HALT instruction, but the Time Base clock and fSUB clock will be on.
* The Data Memory contents and registers will maintain
their present condition.
* The WDT will be cleared and resume counting if the
WDT clock source is selected to come from the fSUB clock and the WDT is enabled. The WDT will stop if its clock source originates from the system clock.
* The I/O ports will maintain their present conditions. * In the status register, the Power Down flag, PDF, will
be set and the Watchdog time-out flag, TO, will be cleared.
Rev. 1.00
36
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
Wake-up After the system enters the SLEEP or IDLE Mode, it can be woken up from one of various sources listed as follows:
* An external reset * An external falling edge on Port A * A system interrupt * A WDT overflow
Programming Considerations The high speed and low speed oscillators both use the same SST counter. For example, if the system is woken up from the SLEEP0 Mode and both the HIRC and LXT oscillators need to start-up from an off state. The LXT oscillator uses the SST counter after HIRC oscillator has finished its SST period.
* If the device is woken up from the SLEEP0 Mode to
If the system is woken up by an external reset, the device will experience a full system reset, however, if the device is woken up by a WDT overflow, a Watchdog Timer reset will be initiated. Although both of these wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the TO and PDF flags. The PDF flag is cleared by a system power-up or executing the clear Watchdog Timer instructions and is set when executing the HALT instruction. The TO flag is set if a WDT time-out occurs, and causes a wake-up that only resets the Program Counter and Stack Pointer, the other flags remain in their original status. Each pin on Port A can be setup using the PAWU register to permit a negative transition on the pin to wake-up the system. When a Port A pin wake-up occurs, the program will resume execution at the instruction following the HALT instruction. If the system is woken up by an interrupt, then two possible situations may occur. The first is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the HALT instruction. In this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is finally enabled or when a stack level becomes free. The other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. If an interrupt request flag is set high before entering the SLEEP or IDLE Mode, the wake-up function of the related interrupt will be disabled.
the NORMAL Mode, the high speed system oscillator needs an SST period. The device will execute first instruction after HTO is 1. At this time, the LXT oscillator may not be stability if fSUB is from LXT oscillator. The same situation occurs in the power-on state. The LXT oscillator is not ready yet when the first instruction is executed.
* If the device is woken up from the SLEEP1 Mode to
NORMAL Mode, and the system clock source is from HXT oscillator and FSTEN is 1, the system clock can be switched to the LIRC oscillator after wake up.
* There are peripheral functions, such as WDT, TMs
and SIM, for which the fSYS is used. If the system clock source is switched from fH to fL, the clock source to the peripheral functions mentioned above will change accordingly.
* The on/off condition of fSUB and fS depends upon
whether the WDT is enabled or disabled as the WDT clock source is selected from fSUB.
Rev. 1.00
37
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
Watchdog Timer
The Watchdog Timer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. Watchdog Timer Clock Source The Watchdog Timer clock source is provided by the internal clock, fS, which is in turn supplied by one of two sources selected by configuration option: fSUB or fSYS/4. The fSUB clock can be sourced from either the LXT or LIRC oscillators, again chosen via a configuration option. The Watchdog Timer source clock is then subdivided by a ratio of 28 to 215 to give longer timeouts, the actual value being chosen using the WS2~WS0 bits in the WDTC register. The LIRC internal oscillator has an approximate period of 32kHz at a supply voltage of 5V. However, it should be noted that this specified internal clock period can vary with VDD, temperature and process variations. The LXT oscillator is supplied by an external 32.768kHz crystal. The other Watchdog Timer clock source option is the fSYS/4 clock. The Watchdog Timer clock source can originate from its own internal LIRC oscillator, the LXT oscillator or fSYS/4. It is divided by a value of 28 to 215, using the WS2~WS0 bits in the WDTC register to obtain the required Watchdog Timer time-out period. Watchdog Timer Control Register A single register, WDTC, controls the required timeout period as well as the enable/disable operation. This register together with several configuration options control the overall operation of the Watchdog Timer.
* WDTC Register
Bit Name R/W POR Bit 7
7 FSYSON R/W 0
6 WS2 R/W 1
5 WS1 R/W 1
4 WS0 R/W 1
3 WDTEN3 R/W 1
2 WDTEN2 R/W 0
1 WDTEN1 R/W 1
0 WDTEN0 R/W 0
FSYSON: fSYS Control in IDLE Mode 0: Disable 1: Enable WS2, WS1, WS0 : WDT time-out period selection 000: 256/fS 001: 512/fS 010: 1024/fS 011: 2048/fS 100: 4096/fS 101: 8192/fS 110: 16384/fS 111: 32768/fS These three bits determine the division ratio of the Watchdog Timer source clock, which in turn determines the timeout period.
Bit 6 ~ 4
Bit 3 ~ 0
WDTEN3, WDTEN2, WDTEN1, WDTEN0 : WDT Software Control 1010: Disable Other: Enable
Rev. 1.00
38
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
Watchdog Timer Operation The Watchdog Timer operates by providing a device reset when its timer overflows. This means that in the application program and during normal operation the user has to strategically clear the Watchdog Timer before it overflows to prevent the Watchdog Timer from executing a reset. This is done using the clear watchdog instructions. If the program malfunctions for whatever reason, jumps to an unkown location, or enters an endless loop, these clear instructions will not be executed in the correct manner, in which case the Watchdog Timer will overflow and reset the device. Some of the Watchdog Timer options, such as enable/disable, clock source selection and clear instruction type are selected using configuration options. In addition to a configuration option to enable/disable the Watchdog Timer, there are also four bits, WDTEN3~WDTEN0, in the WDTC register to offer an additional enable/disable control of the Watchdog Timer. To disable the Watchdog Timer, as well as the configuration option being set to disable, the WDTEN3~WDTEN0 bits must also be set to a specific value of 1010. Any other values for these bits will keep the Watchdog Timer enabled, irrespective of the configuration enable/disable setting. After power on these bits will have the value of 1010. If the Watchdog Timer is used it is recommended that they are set to a value of 0101 for maximum noise immunity. Note that if the Watchdog Timer has been disabled, then any instruction relating to its operation will result in no operation. WDT Configuration Option WDT Enable WDT Disable WDT Disable WDTEN3~ WDTEN0 Bits xxxx Except 1010 1010 WDT Enable Enable Disable bit TO. However, if the system is in the SLEEP or IDLE Mode, when a Watchdog Timer time-out occurs, the TO bit in the status register will be set and only the Program Counter and Stack Pointer will be reset. Three methods can be adopted to clear the contents of the Watchdog Timer. The first is an external hardware reset, which means a low level on the RES pin, the second is using the Watchdog Timer software clear instructions and the third is via a HALT instruction. There are two methods of using software instructions to clear the Watchdog Timer, one of which must be chosen by configuration option. The first option is to use the single CLR WDT instruction while the second is to use the two commands CLR WDT1 and CLR WDT2. For the first option, a simple execution of CLR WDT will clear the WDT while for the second option, both CLR WDT1 and CLR WDT2 must both be executed alternately to successfully clear the Watchdog Timer. Note that for this second option, if CLR WDT1 is used to clear the Watchdog Timer, successive executions of this instruction will have no effect, only the execution of a CLR WDT2 instruction will clear the Watchdog Timer. Similarly after the CLR WDT2 instruction has been executed, only a successive CLR WDT1 instruction can clear the Watchdog Timer. The maximum time out period is when the 215 division ratio is selected. As an example, with a 32.768kHz LXT oscillator as its source clock, this will give a maximum watchdog period of around 1 second for the 215 division ratio, and a minimum timeout of 7.8ms for the 28 division ration. If the fSYS/4 clock is used as the Watchdog Timer clock source, it should be noted that when the system enters the SLEEP or IDLE0 Mode, then the instruction clock is stopped and the Watchdog Timer may lose its protecting purposes. For systems that operate in noisy environments, using the fSUB clock source is strongly recommended.
Watchdog Timer Enable/Disable Control Under normal program operation, a Watchdog Timer time-out will initialise a device reset and set the status
CLR CLR
W D T 1 F la g W D T 2 F la g
C le a r W D T T y p e C o n fig u r a tio n O p tio n CLR
8
1 o r 2 In s tr u c tio n s
fS
LXT M U X L IR C
YS
/4
M fS
UB
U X
fS
8 - s ta g e D iv id e r
fS /2
W D T P r e s c a le r
C o n fig u r a tio n O p tio n C o n fig u r a tio n O p tio n
8 -to -1 M U X W S2~W S0 (fS /2 8 ~ fS /2 15)
W D T T im e - o u t (2 8 /fS ~ 2 15/fS )
Watchdog Timer
Rev. 1.00
39
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
Reset and Initialisation
A reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. The most important reset condition is after power is first applied to the microcontroller. In this case, internal circuitry will ensure that the microcontroller, after a short delay, will be in a well defined state and ready to execute the first program instruction. After this power-on reset, certain important internal registers will be set to defined states before the program commences. One of these registers is the Program Counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest Program Memory address. In addition to the power-on reset, situations may arise where it is necessary to forcefully apply a reset condition when the microcontroller is running. One example of this is where after power has been applied and the microcontroller is already running, the RES line is forcefully pulled low. In such a case, known as a normal operation reset, some of the microcontroller registers remain unchanged allowing the microcontroller to proceed with normal operation after the reset line is allowed to return high. Another type of reset is when the Watchdog Timer overflows and resets the microcontroller. All types of reset operations result in different register conditions being setup. Another reset exists in the form of a Low Voltage Reset, LVR, where a full reset, similar to the RES reset is implemented in situations where the power supply voltage falls below a certain threshold. Reset Functions There are five ways in which a microcontroller reset can occur, through events occurring both internally and externally:
* Power-on Reset * RES Pin
As the reset pin is shared with PB.0, the reset function must be selected using a configuration option. Although the microcontroller has an internal RC reset function, if the VDD power supply rise time is not fast enough or does not stabilise quickly at power-on, the internal reset function may be incapable of providing proper reset operation. For this reason it is recommended that an external RC network is connected to the RES pin, whose additional time delay will ensure that the RES pin remains low for an extended period to allow the power supply to stabilise. During this time delay, normal operation of the microcontroller will be inhibited. After the RES line reaches a certain voltage value, the reset delay time tRSTD is invoked to provide an extra delay time after which the microcontroller will begin normal operation. The abbreviation SST in the figures stands for System Start-up Timer. For most applications a resistor connected between VDD and the RES pin and a capacitor connected between VSS and the RES pin will provide a suitable external reset circuit. Any wiring connected to the RES pin should be kept as short as possible to minimise any stray noise interference. For applications that operate within an environment where more noise is present the Enhanced Reset Circuit shown is recommended.
V 0 .0 1 m F * * 1N4148*
DD
VDD 10kW ~ 100kW P B 0 /R E S
300W * 0 .1 ~ 1 m F
VSS
Note:
The most fundamental and unavoidable reset is the one that occurs after power is first applied to the microcontroller. As well as ensuring that the Program Memory begins execution from the first memory address, a power-on reset also ensures that certain other registers are preset to known conditions. All the I/O port and port control registers will power up in a high condition ensuring that all pins will be first set to inputs.
VDD RES In te rn a l R e s e t 0 .9 V
DD
* It is recommended that this component is added for added ESD protection ** It is recommended that this component is added in environments where power line noise is significant External RES Circuit
More information regarding external reset circuits is located in Application Note HA0075E on the Holtek website.
t RR
SS TT DD ++
t SS
SS TT
Note: tRSTD is power-on delay, typical time=100ms Power-On Reset Timing Chart
Rev. 1.00
40
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
Pulling the RES Pin low using external hardware will also execute a device reset. In this case, as in the case of other resets, the Program Counter will reset to zero and program execution initiated from this point.
RES 0 .4 V 0 .9 V
DD DD
Program Counter and the Stack Pointer will be cleared to 0 and the TO flag will be set to 1. Refer to the A.C. Characteristics for tSST details. Note: The tSST is 15~16 clock cycles if the system clock source is provided by ERC or HIRC. The tSST is 1024 clock for HXT or LXT. The tSST is 1~2 clock for LIRC.
tR
In te rn a l R e s e t
STD
+
tS
ST
Reset Initial Conditions RES Reset Timing Chart The different types of reset described affect the reset flags in different ways. These flags, known as PDF and TO are located in the status register and are controlled by various microcontroller operations, such as the SLEEP or IDLE Mode function or Watchdog Timer. The reset flags are shown in the table: TO PDF 0 u 1 1 0 u u 1 RESET Conditions Power-on reset RES or LVR reset during NORMAL or SLOW Mode operation WDT time-out reset during NORMAL or SLOW Mode operation WDT time-out reset during IDLE or SLEEP Mode operation
Note: tRSTD is power-on delay, typical time=100ms
* Low Voltage Reset - LVR
The microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device, which is selected via a configuration option. If the supply voltage of the device drops to within a range of 0.9V~VLVR such as might occur when changing the battery, the LVR will automatically reset the device internally. The LVR includes the following specifications: For a valid LVR signal, a low voltage, i.e., a voltage in the range between 0.9V~VLVR must exist for greater than the value tLVR specified in the A.C. characteristics. If the low voltage state does not exceed tLVR, the LVR will ignore it and will not perform a reset function. One of a range of specified voltage values for VLVR can be selected using configuration options.
LVR
Note: u stands for unchanged
tR
STD +
tS
ST
In te rn a l R e s e t
Note: tRSTD is power-on delay, typical time=100ms Low Voltage Reset Timing Chart
* Watchdog Time-out Reset during Normal Operation
The following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. Item Program Counter Interrupts WDT Timer/Event Counter Input/Output Ports Stack Pointer Condition After RESET Reset to zero All interrupts will be disabled Clear after reset, WDT begins counting Timer Counter will be turned off I/O ports will be setup as inputs, and AN0~AN3 as A/D input pins Stack Pointer will point to the top of the stack
The Watchdog time-out Reset during normal operation is the same as a hardware RES pin reset except that the Watchdog time-out flag TO will be set to 1.
W D T T im e - o u t
tR
In te rn a l R e s e t
STD
+
tS
ST
Note: tRSTD is power-on delay, typical time=100ms WDT Time-out Reset during Normal Operation Timing Chart
* Watchdog Time-out Reset during SLEEP or IDLE
Mode The Watchdog time-out Reset during SLEEP or IDLE Mode is a little different from other kinds of reset. Most of the conditions remain unchanged except that the
W D T T im e - o u t
tS
In te rn a l R e s e t
ST
WDT Time-out Reset during SLEEP or IDLE Timing Chart
Rev. 1.00
41
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
The different kinds of resets all affect the internal registers of the microcontroller in different ways. To ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. The following table describes how each type of reset affects each of the microcontroller internal registers. Note that where more than one package type exists the table will reflect the situation for the larger package type.
* HT66F03 Register
Register MP0 MP1 BP ACC PCL TBLP TBLH TBHP STATUS SMOD LVDC INTEG INTC0 INTC1 INTC2 MFI0 MFI2 PA PAC PAPU PAWU PRM WDTC TBC EEA EED EEC ADRL (ADRFS=0) ADRL (ADRFS=1) ADRH (ADRFS=0) ADRH (ADRFS=1) ADCR0 ADCR1 ACERL
Reset (Power-on) xxxx xxxx xxxx xxxx ---- ---0 xxxx xxxx 0000 0000 xxxx xxxx --xx xxxx ---- --xx --00 xxxx 0000 0011 --00 -000 ---- --00 -000 0000 0000 0000 ---0 ---0 0000 0000 --00 --00 1111 1111 1111 1111 0000 0000 0000 0000 0101 0000 0111 1010 0011 0111 --xx xxxx xxxx xxxx ---- 0000 xxxx ---xxxx xxxx xxxx xxxx ---- xxxx 0110 --00 00-0 -000 ---- 1111
RES or LVR Reset xxxx xxxx xxxx xxxx ---- ---0 uuuu uuuu 0000 0000 uuuu uuuu --uu uuuu ---- --uu --uu uuuu 0000 0011 --00 -000 ---- --00 -000 0000 0000 0000 ---0 ---0 0000 0000 --00 --00 1111 1111 1111 1111 0000 0000 0000 0000 0101 0000 0111 1010 0011 0111 --xx xxxx xxxx xxxx ---- 0000 xxxx ---xxxx xxxx xxxx xxxx ---- xxxx 0110 --00 00-0 -000 ---- 1111
WDT Time-out (Normal Operation) xxxx xxxx xxxx xxxx ---- ---0 uuuu uuuu 0000 0000 uuuu uuuu --uu uuuu ---- --uu --1u uuuu 0000 0011 --00 -000 ---- --00 -000 0000 0000 0000 ---0 ---0 0000 0000 --00 --00 1111 1111 1111 1111 0000 0000 0000 0000 0101 0000 0111 1010 0011 0111 --xx xxxx xxxx xxxx ---- 0000 xxxx ---xxxx xxxx xxxx xxxx ---- xxxx 0110 --00 00-0 -000 ---- 1111
WDT Time-out (IDLE) uuuu uuuu uuuu uuuu ---- ---u uuuu uuuu 0000 0000 uuuu uuuu --uu uuuu ---- --uu --11 uuuu uuuu uuuu --uu -uuu ---- --uu -uuu uuuu uuuu uuuu ---u ---u uuuu uuuu --uu --uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --uu uuuu uuuu uuuu ---- uuuu uuuu ---uuuu uuuu uuuu uuuu ---- uuuu uuuu --uu uu-u -uuu ---- uuuu
Rev. 1.00
42
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
Register CPC TM0C0 TM0C1 TM0DL TM0DH TM0AL TM0AH TM1C0 TM1C1 TM1DL TM1DH TM1AL TM1AH Note: Reset (Power-on) 1000 0--1 0000 0000 0000 0000 0000 0000 ---- --00 0000 0000 ---- --00 0000 0000 0000 0000 0000 0000 ---- --00 0000 0000 ---- --00 RES or LVR Reset 1000 0--1 0000 0000 0000 0000 0000 0000 ---- --00 0000 0000 ---- --00 0000 0000 0000 0000 0000 0000 ---- --00 0000 0000 ---- --00 WDT Time-out (Normal Operation) 1000 0--1 0000 0000 0000 0000 0000 0000 ---- --00 0000 0000 ---- --00 0000 0000 0000 0000 0000 0000 ---- --00 0000 0000 ---- --00 WDT Time-out (IDLE) uuuu u--u uuuu uuuu uuuu uuuu uuuu uuuu ---- --uu uuuu uuuu ---- --uu uuuu uuuu uuuu uuuu uuuu uuuu ---- --uu uuuu uuuu ---- --uu
u stands for unchanged x stands for unknown - stands for unimplemented
Rev. 1.00
43
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
* HT66F04 Register
Register MP0 MP1 BP ACC PCL TBLP TBLH TBHP STATUS SMOD LVDC INTEG INTC0 INTC1 INTC2 MFI0 MFI1 MFI2 PA PAC PAPU PAWU PRM WDTC TBC EEA EED EEC ADRL (ADRFS=0) ADRL (ADRFS=1) ADRH (ADRFS=0) ADRH (ADRFS=1) ADCR0 ADCR1 ACERL CPC TM0C0 TM0C1
Reset (Power-on) xxxx xxxx xxxx xxxx ---- ---0 xxxx xxxx 0000 0000 xxxx xxxx -xxx xxxx ---- -xxx --00 xxxx 0000 0011 --00 -000 ---- --00 -000 0000 0000 0000 ---0 ---0 0000 0000 -000 0000 --00 --00 1111 1111 1111 1111 0000 0000 0000 0000 0101 0000 0111 1010 0011 0111 --xx xxxx xxxx xxxx ---- 0000 xxxx ---xxxx xxxx xxxx xxxx ---- xxxx 0110 --00 00-0 -000 ---- 1111 1000 0--1 0000 0000 0000 0000
RES or LVR Reset xxxx xxxx xxxx xxxx ---- ---0 uuuu uuuu 0000 0000 uuuu uuuu -uuu uuuu ---- -uuu --uu uuuu 0000 0011 --00 -000 ---- --00 -000 0000 0000 0000 ---0 ---0 0000 0000 -000 0000 --00 --00 1111 1111 1111 1111 0000 0000 0000 0000 0101 0000 0111 1010 0011 0111 --xx xxxx xxxx xxxx ---- 0000 xxxx ---xxxx xxxx xxxx xxxx ---- xxxx 0110 --00 00-0 -000 ---- 1111 1000 0--1 0000 0000 0000 0000
WDT Time-out (Normal Operation) xxxx xxxx xxxx xxxx ---- ---0 uuuu uuuu 0000 0000 uuuu uuuu -uuu uuuu ---- -uuu --1u uuuu 0000 0011 --00 -000 ---- --00 -000 0000 0000 0000 ---0 ---0 0000 0000 -000 0000 --00 --00 1111 1111 1111 1111 0000 0000 0000 0000 0101 0000 0111 1010 0011 0111 --xx xxxx xxxx xxxx ---- 0000 xxxx ---xxxx xxxx xxxx xxxx ---- xxxx 0110 --00 00-0 -000 ---- 1111 1000 0--1 0000 0000 0000 0000
WDT Time-out (IDLE) uuuu uuuu uuuu uuuu ---- ---u uuuu uuuu 0000 0000 uuuu uuuu -uuu uuuu ---- -uuu --11 uuuu uuuu uuuu --uu -uuu ---- --uu -uuu uuuu uuuu uuuu ---u ---u uuuu uuuu -uuu uuuu --uu --uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --uu uuuu uuuu uuuu ---- uuuu uuuu ---uuuu uuuu uuuu uuuu ---- uuuu uuuu --uu uu-u -uuu ---- uuuu uuuu u--u uuuu uuuu uuuu uuuu
Rev. 1.00
44
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
Register TM0DL TM0DH TM0AL TM0AH TM1C0 TM1C1 TM1DL TM1DH TM1AL TM1AH TM2C0 TM2C1 TM2DL TM2DH TM2AL TM2AH TM2BL TM2BH Note: Reset (Power-on) 0000 0000 ---- --00 0000 0000 ---- --00 0000 0000 0000 0000 0000 0000 ---- --00 0000 0000 ---- --00 0000 0000 0000 0000 0000 0000 ---- --00 0000 0000 ---- --00 0000 0000 00-- ---RES or LVR Reset 0000 0000 ---- --00 0000 0000 ---- --00 0000 0000 0000 0000 0000 0000 ---- --00 0000 0000 ---- --00 0000 0000 0000 0000 0000 0000 ---- --00 0000 0000 ---- --00 0000 0000 00-- ---WDT Time-out (Normal Operation) 0000 0000 ---- --00 0000 0000 ---- --00 0000 0000 0000 0000 0000 0000 ---- --00 0000 0000 ---- --00 0000 0000 0000 0000 0000 0000 ---- --00 0000 0000 ---- --00 0000 0000 00-- ---WDT Time-out (IDLE) uuuu uuuu ---- --uu uuuu uuuu ---- --uu uuuu uuuu uuuu uuuu uuuu uuuu ---- --uu uuuu uuuu ---- --uu uuuu uuuu uuuu uuuu uuuu uuuu ---- --uu uuuu uuuu ---- --uu uuuu uuuu uu-- ----
u stands for unchanged x stands for unknown - stands for unimplemented
Rev. 1.00
45
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
* HT68F03 Register
Register MP0 MP1 BP ACC PCL TBLP TBLH TBHP STATUS SMOD LVDC INTEG INTC0 INTC1 INTC2 MFI0 MFI2 PA PAC PAPU PAWU PRM WDTC TBC EEA EED EEC CPC TM0C0 TM0C1 TM0DL TM0DH TM0AL TM0AH TM1C0 TM1C1 TM1DL TM1DH TM1AL TM1AH Note:
Reset (Power-on) xxxx xxxx xxxx xxxx ---- ---0 xxxx xxxx 0000 0000 xxxx xxxx --xx xxxx ---- --xx --00 xxxx 0000 0011 --00 -000 ---- --00 -000 0000 0-00 0-00 ---0 ---0 0000 0000 --00 --00 1111 1111 1111 1111 0000 0000 0000 0000 0101 0000 0111 1010 0011 0111 --xx xxxx xxxx xxxx ---- 0000 1000 0--1 0000 0000 0000 0000 0000 0000 ---- --00 0000 0000 ---- --00 0000 0000 0000 0000 0000 0000 ---- --00 0000 0000 ---- --00
RES or LVR Reset xxxx xxxx xxxx xxxx ---- ---0 uuuu uuuu 0000 0000 uuuu uuuu --uu uuuu ---- --uu --uu uuuu 0000 0011 --00 -000 ---- --00 -000 0000 0-00 0-00 ---0 ---0 0000 0000 --00 --00 1111 1111 1111 1111 0000 0000 0000 0000 0101 0000 0111 1010 0011 0111 --xx xxxx xxxx xxxx ---- 0000 1000 0--1 0000 0000 0000 0000 0000 0000 ---- --00 0000 0000 ---- --00 0000 0000 0000 0000 0000 0000 ---- --00 0000 0000 ---- --00
WDT Time-out (Normal Operation) xxxx xxxx xxxx xxxx ---- ---0 uuuu uuuu 0000 0000 uuuu uuuu --uu uuuu ---- --uu --1u uuuu 0000 0011 --00 -000 ---- --00 -000 0000 0-00 0-00 ---0 ---0 0000 0000 --00 --00 1111 1111 1111 1111 0000 0000 0000 0000 0101 0000 0111 1010 0011 0111 --xx xxxx xxxx xxxx ---- 0000 1000 0--1 0000 0000 0000 0000 0000 0000 ---- --00 0000 0000 ---- --00 0000 0000 0000 0000 0000 0000 ---- --00 0000 0000 ---- --00
WDT Time-out (IDLE) uuuu uuuu uuuu uuuu ---- ---u uuuu uuuu 0000 0000 uuuu uuuu --uu uuuu ---- --uu --11 uuuu uuuu uuuu --uu -uuu ---- --uu -uuu uuuu u-uu u-uu ---u ---u uuuu uuuu --uu --uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --uu uuuu uuuu uuuu ---- uuuu uuuu u--u uuuu uuuu uuuu uuuu uuuu uuuu ---- --uu uuuu uuuu ---- --uu uuuu uuuu uuuu uuuu uuuu uuuu ---- --uu uuuu uuuu ---- --uu
u stands for unchanged x stands for unknown - stands for unimplemented 46 April 16, 2010
Rev. 1.00
HT66F03/HT66F04/HT68F03/HT68F04
* HT68F04 Register
Register MP0 MP1 BP ACC PCL TBLP TBLH TBHP STATUS SMOD LVDC INTEG INTC0 INTC1 INTC2 MFI0 MFI2 PA PAC PAPU PAWU PRM WDTC TBC EEA EED EEC CPC TM0C0 TM0C1 TM0DL TM0DH TM0AL TM0AH TM1C0 TM1C1 TM1DL TM1DH TM1AL TM1AH Note:
Reset (Power-on) xxxx xxxx xxxx xxxx ---- ---0 xxxx xxxx 0000 0000 xxxx xxxx -xxx xxxx ---- -xxx --00 xxxx 0000 0011 --00 -000 ---- --00 -000 0000 0-00 0-00 ---0 ---0 0000 0000 --00 --00 1111 1111 1111 1111 0000 0000 0000 0000 0101 0000 0111 1010 0011 0111 --xx xxxx xxxx xxxx ---- 0000 1000 0--1 0000 0000 0000 0000 0000 0000 ---- --00 0000 0000 ---- --00 0000 0000 0000 0000 0000 0000 ---- --00 0000 0000 ---- --00
RES or LVR Reset xxxx xxxx xxxx xxxx ---- ---0 uuuu uuuu 0000 0000 uuuu uuuu -uuu uuuu ---- -uuu --uu uuuu 0000 0011 --00 -000 ---- --00 -000 0000 0-00 0-00 ---0 ---0 0000 0000 --00 --00 1111 1111 1111 1111 0000 0000 0000 0000 0101 0000 0111 1010 0 .0 1 1 0 1 1 1 --xx xxxx xxxx xxxx ---- 0000 1000 0--1 0000 0000 0000 0000 0000 0000 ---- --00 0000 0000 ---- --00 0000 0000 0000 0000 0000 0000 ---- --00 0000 0000 ---- --00
WDT Time-out (Normal Operation) xxxx xxxx xxxx xxxx ---- ---0 uuuu uuuu 0000 0000 uuuu uuuu -uuu uuuu ---- -uuu --1u uuuu 0000 0011 --00 -000 ---- --00 -000 0000 0-00 0-00 ---0 ---0 0000 0000 --00 --00 1111 1111 1111 1111 0000 0000 0000 0000 0101 0000 0111 1010 0011 0111 --xx xxxx xxxx xxxx ---- 0000 1000 0--1 0000 0000 0000 0000 0000 0000 ---- --00 0000 0000 ---- --00 0000 0000 0000 0000 0000 0000 ---- --00 0000 0000 ---- --00
WDT Time-out (IDLE) uuuu uuuu uuuu uuuu ---- ---u uuuu uuuu 0000 0000 uuuu uuuu -uuu uuuu ---- -uuu --11 uuuu uuuu uuuu --uu -uuu ---- --uu -uuu uuuu u-uu u-uu ---u ---u uuuu uuuu --uu --uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --uu uuuu uuuu uuuu ---- uuuu uuuu u--u uuuu uuuu uuuu uuuu uuuu uuuu ---- --uu uuuu uuuu ---- --uu uuuu uuuu uuuu uuuu uuuu uuuu ---- --uu uuuu uuuu ---- --uu
u stands for unchanged x stands for unknown - stands for unimplemented
Rev. 1.00
47
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
Input/Output Ports
Holtek microcontrollers offer considerable flexibility on their I/O ports. With the input or output designation of every pin fully under user program control, pull-high selections for all ports and wake-up selections on certain pins, the user is provided with an I/O structure to meet the needs of a wide range of application possibilities. The device provides bidirectional input/output lines labeled with port names PA. These I/O ports are mapped to the RAM Data Memory with specific addresses as shown in the Special Purpose Data Memory table. All of these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, which means the inputs must be ready at the T2 rising edge of instruction MOV A,[m], where m denotes the port address. For output operation, all the data is latched and remains unchanged until the output latch is rewritten.
* I/O Register List
Register Name PAWU PAPU PA PAC
Bit 7 D7 D7 D7 D7 6 D6 D6 D6 D6 5 D5 D5 D5 D5 4 D4 D4 D4 D4 3 D3 D3 D3 D3 2 D2 D2 D2 D2 1 D1 D1 D1 D1 0 D0 D0 D0 D0
Pull-high Resistors Many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor. To eliminate the need for these external resistors, all I/O pins, when configured as an input have the capability of being connected to an internal pull-high resistor. These pull-high resistors are selected using the register PAPU, and are implemented using weak PMOS transistors.
* PAPU Register
Bit Name R/W POR Port A Wake-up
7 D7 R/W 0
6 D6 R/W 0
5 D5 R/W 0
4 D4 R/W 0
3 D3 R/W 0
2 D2 R/W 0
1 D1 R/W 0
0 D0 R/W 0
The HALT instruction forces the microcontroller into the SLEEP or IDLE Mode which preserves power, a feature that is important for battery and other low-power applications. Various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the Port A pins from high to low. This function is especially suitable for applications that can be woken up via external switches. Each pin on Port A can be selected individually to have this wake-up feature using the PAWU register.
* PAWU Register
Bit Name R/W POR Bit 7~0
7 D7 R/W 0
6 D6 R/W 0
5 D5 R/W 0
4 D4 R/W 0
3 D3 R/W 0
2 D2 R/W 0
1 D1 R/W 0
0 D0 R/W 0
PAWU: Port A bit 7 ~ bit 0 Wake-up Control 0: Disable 1: Enable
Rev. 1.00
48
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
I/O Port Control Register The I/O port has its own control register known as PAC, to control the input/output configuration. With this control register, each CMOS output or input can be reconfigured dynamically under software control. Each pin of the I/O port is directly mapped to a bit in its associated port control register. For the I/O pin to function as an input, the corresponding bit of the control register must be written as a 1. This will then allow the logic state of the input pin to be directly read by instructions. When the corresponding bit of the control register is written as a 0, the I/O pin will be setup as a CMOS output. If the pin is currently setup as an output, instructions can still be used to read the output register. However, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin.
* PAC Register
Bit Name R/W POR Bit 7~0
7 D7 R/W 1
6 D6 R/W 1
5 D5 R/W 1
4 D4 R/W 1
3 D3 R/W 1
2 D2 R/W 1
1 D1 R/W 1
0 D0 R/W 1
I/O Port bit 7 ~ bit 0 Input/Output Control 0: Output 1: Input
Pin-remapping Functions The flexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. Limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions, many of these difficulties can be overcome. The way in which the pin function of each pin is selected is different for each function and a priority order is established where more than one pin function is selected simultaneously. Additionally there is a PRM register to establish certain pin functions. Generally speaking, the analog function has higher priority than the digital function. However, if more than two analog functions are enabled and the analog signal input comes from the same external pin, the analog input will be internally connected to all of these active analog functional modules. Pin-remapping Registers The limited number of supplied pins in a package can impose restrictions on the amount of functions a certain device can contain. However by allowing the same pins to share several different functions and providing a means of function selection, a wide range of different functions can be incorporated into even relatively small package sizes.
* Pin-remapping Register List
Register Name PRM
Bit 7 PRML3 6 PRML2 5 PRML1 4 PRML0 3 3/4 2 PRMS2 1 PRMS1 0 PRMS0
Rev. 1.00
49
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
* PRM Register
HT66F03/HT68F03/HT68F04 Bit Name R/W POR 7 PRML3 R/W 0 6 PRML2 R/W 1 5 PRML1 R/W 0 4 PRML0 R/W 1 3 3/4 3/4 3/4 2 PRMS2 R/W 0 1 PRMS1 R/W 0 0 PRMS0 R/W 0
Bit 7~4
PRML3~PRML0: pin-remapping function lock bits (default: 0101) 1010: PRM register write operation is enabled Others: PRM register write operation is disabled Unimplemented, read as 0 PRMS2: INT/TCK1 pin-remapping function selection bit 1: INT on PA7, TCK1 on PA7. 0: INT on PA3, TCK1 on PA3. PRMS1~PRMS0: pin-remapping function selection bits 0x: TP0 on PA3, TP1/TCK0 on PA4. 10: TP0 on PA5, TP1/TCK0 on PA6. 11: TP0 on PA2, TP1/TCK0 on PA7.
Bit 3 Bit 2
Bit 1~0
* HT66F04
Bit Name R/W POR Bit 7~4
7 PRML3 R/W 0
6 PRML2 R/W 1
5 PRML1 R/W 0
4 PRML0 R/W 1
3 3/4 3/4 3/4
2 PRMS2 R/W 0
1 PRMS1 R/W 0
0 PRMS0 R/W 0
PRML3~PRML0: pin-remapping function lock bits (default: 0101) 1010: PRM register write operation is enabled Others: PRM register write operation is disabled Unimplemented, read as 0 PRMS2: INT/TCK1 pin-remapping function selection bit 1: INT on PA7, TCK1 on PA7. 0: INT on PA3, TCK1 on PA3. PRMS1~PRMS0: pin-remapping function selection bits 00: TP0/TCK2 on PA3, TP1/TCK0 on PA4, TP2B on PA5, TP2A on PA6 01: TP0/TCK2 on PA3, TP1/TCK0 on PA4, TP2B on PA0, TP2A on PA1 10: TP0/TCK2 on PA5, TP1/TCK0 on PA6, TP2B on PA2, TP2A on PA7 11: TP0/TCK2 on PA2, TP1/TCK0 on PA7, TP2B on PA5, TP2A on PA6
Bit 3 Bit 2
Bit 1~0
I/O Pin Structures The accompanying diagrams illustrate the internal structures of some generic I/O pin types. As the exact logical construction of the I/O pin will differ from these drawings, they are supplied as a guide only to assist with the functional understanding of the I/O pins. The wide range of pin-shared structures does not permit all types to be shown. Programming Considerations Within the user program, one of the first things to consider is port initialisation. After a reset, all of the I/O data and port control register will be set high. This means that all I/O pins will default to an input state, the level of which
depends on the other connected circuitry and whether pull-high selections have been chosen. If the port control register, PAC, is then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data register, PA, is first programmed. Selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register or by programming individual bits in the port control register using the SET [m].i and CLR [m].i instructions. Note that when using these bit control instructions, a read-modify-write operation takes place. The microcontroller must first read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports.
Rev. 1.00
50
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
The power-on reset condition of the A/D converter control registers ensures that any A/D input pins - which are always shared with other I/O functions - will be setup as analog inputs after a reset. Although these pins will be configured as A/D inputs after a reset, the A/D converter will not be switched on. It is therefore important to note that if it is required to use these pins as I/O digital input pins or as other functions, the A/D converter control registers must be correctly programmed to remove the A/D function. Note also that as the A/D channel is enabled, any internal pull-high resistor connections will be removed. Port A has the additional capability of providing wake-up functions. When the device is in the SLEEP or IDLE Mode, various methods are available to wake the device up. One of these is a high to low transition of any of the Port A pins. Single or multiple pins on Port A can be setup to have this function.
C o n tr o l B it
D a ta B u s
D
Q CK S Q
P u ll- H ig h R e g is te r S e le c t
V
DD
W eak P u ll- u p
W r ite C o n tr o l R e g is te r C h ip R e s e t R e a d C o n tr o l R e g is te r
I/O D a ta B it Q D CK Q S M U X P A o n ly
p in
W r ite D a ta R e g is te r
R e a d D a ta R e g is te r S y s te m W a k e -u p
W a k e - u p S e le c t
Generic Input/Output Structure
V C o n tr o l B it Q D CK S Q P u ll- H ig h R e g is te r S e le c t
DD
D a ta B u s W r ite C o n tr o l R e g is te r C h ip R e s e t R e a d C o n tr o l R e g is te r
W eak P u ll- u p
A /D D a ta B it Q D CK S Q
M U X
In p u t P in s
W r ite D a ta R e g is te r
R e a d D a ta R e g is te r
A n a lo g In p u t S e le c to r T o A /D C o n v e rte r AC S3~ACS0
A/D Input/Output Structure Rev. 1.00 51 April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
Timer Modules - TM
One of the most fundamental functions in any microcontroller device is the ability to control and measure time. To implement time related functions each device includes several Timer Modules, abbreviated to the name TM. The TMs are multi-purpose timing units and serve to provide operations such as Timer/Counter, Input Capture, Compare Match Output and Single Pulse Output as well as being the functional unit for the generation of PWM signals. Each of the TMs has either two or three individual interrupts. The addition of input and output pins for each TM ensures that users are provided with timing units with a wide and flexible range of features. The common features of the different TM types are described here with more detailed information provided in the individual Compact, Standard and Enhanced TM sections. Introduction The devices contain from two to four TMs depending upon which device is selected with each TM having a reference name of TM0, TM1 and TM2. Each individual TM can be categorised as a certain type, namely Compact Type TM, Standard Type TM or Enhanced Type TM. Although similar in nature, the different TM types vary in their feature complexity. The common features to all of the Compact, Standard and Enhanced TMs will be described in this section, the detailed operation regarding each of the TM types will be described in separate sections. The main features and differences between the three types of TMs are summarised in the accompanying table.
Function Timer/Counter I/P Capture Compare Match Output PWM Channels Single Pulse Output PWM Alignment PWM Adjustment Period & Duty
CTM O 3/4 O 1 3/4 Edge Duty or Period TM Function Summary
STM O O O 1 1 Edge Duty or Period
ETM O O O 2 1 Edge & Centre Duty or Period
Each device in the series contains a specific number of either Compact Type, Standard Type and Enhanced Type TM units which are shown in the table together with their individual reference name, TM0~TM2. Device HT66F03/HT68F03/HT68F04 HT66F04 TM0 10-bit CTM 10-bit CTM TM1 10-bit STM 10-bit STM TM2 3/4 10-bit ETM
TM Name/Type Reference
Rev. 1.00
52
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
TM Operation The three different types of TM offer a diverse range of functions, from simple timing operations to PWM signal generation. The key to understanding how the TM operates is to see it in terms of a free running counter whose v a lu e is t h e n c o m p a r ed w i t h t h e v a l u e o f pre-programmed internal comparators. When the free ru n n in g c ount er h a s t he s a m e v al u e a s t h e pre-programmed comparator, known as a compare match situation, a TM interrupt signal will be generated which can clear the counter and perhaps also change the condition of the TM output pin. The internal TM counter is driven by a user selectable clock source, which can be an internal clock or an external pin. TM Clock Source The clock source which drives the main counter in each TM can originate from various sources. The selection of the required clock source is implemented using the TnCK2~TnCK0 bits in the TM control registers. The clock source can be a ratio of either the system clock fSYS or the internal high clock fH, the fTBC clock source or the external TCKn pin. Note that setting these bits to the value 101 will select a reserved clock input, in effect disconnecting the TM clock source. The TCKn pin clock source is used to allow an external signal to drive the TM as an external clock source or for event counting. TM Interrupts The Compact and Standard type TMs each have two internal interrupts, one for each of the internal comparator A or comparator P, which generate a TM interrupt when a compare match condition occurs. As the Enhanced type TM has three internal comparators and comparator A or comparator B or comparator P compare match functions, it consequently has three internal interrupts. When a TM interrupt is generated it can be used to clear the counter and also to change the state of the TM output pin. TM External Pins Each of the TMs, irrespective of what type, has one TM input pin, with the label TCKn. The TM input pin, is essentially a clock source for the TM and is selected using the TnCK2~TnCK0 bits in the TMnC0 register. This external TM input pin allows an external clock source to drive the internal TM. This external TM input pin is shared with other functions but will be connected to the internal TM if selected using the TnCK2~TnCK0 bits. The TM input pin can be chosen to have either a rising or falling active edge. The TMs each have one or more output pins with the label TPn. When the TM is in the Compare Match Output Mode, these pins can be controlled by the TM to switch to a high or low level or to toggle when a compare match situation occurs. The external TPn output pin is also the pin where the TM generates the PWM output waveform. As the TM output pins are pin-shared with other function, the TM output function must first be setup using registers. A single bit in one of the registers determines if its associated pin is to be used as an external TM output pin or if it is to have another function. The number of output pins for each TM type and device is different, the details are provided in the accompanying table.
Device HT66F03/HT68F03/HT68F04 HT66F04
CTM TP0 TP0 TM Output Pins
STM TP1 TP1
ETM 3/4 TP2A, TP2B
Rev. 1.00
53
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
Programming Considerations The TM Counter Registers and the Capture/Compare CCRA and CCRB registers, being either 10-bit or 16-bit, all have a low and high byte structure. The high bytes can be directly accessed, but as the low bytes can only be accessed via an internal 8-bit buffer, reading or writing to these register pairs must be carried out in a specific way. The important point to note is that data transfer to and from the 8-bit buffer and its related low byte only takes place when a write or read operation to its corresponding high byte is executed.
TM Counter Register (Read only)
TMxDL 8-bit Buffer
TMxDH
TMxAL
TMxAH
TM CCRA Register (Read/Write)
TMxBL
TMxBH
Data Bus
TM CCRB Register (Read/Write)
The following steps show the read and write procedures:
* Writing Data to CCRB or CCRA
Step 1. Write data to Low Byte TMxAL or TMxBL - note that here data is only written to the 8-bit buffer. Step 2. Write data to High Byte TMxAH or TMxBH - here data is written directly to the high byte registers and simultaneously data is latched from the 8-bit buffer to the Low Byte registers.
* Reading Data from the Counter Registers and CCRB or CCRA
Step 1. Read data from the High Byte TMxDH, TMxAH or TMxBH - here data is read directly from the High Byte registers and simultaneously data is latched from the Low Byte register into the 8-bit buffer. Step 2. Read data from the Low Byte TMxDL, TMxAL or TMxBL - this step reads data from the 8-bit buffer.
Rev. 1.00
54
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
Compact Type TM
Although the simplest form of the three TM types, the Compact TM type still contains three operating modes, which are Compare Match Output, Timer/Event Counter and PWM Output modes. The Compact TM can also be controlled with an external input pin and can drive one or two external output pin. These two external output pins can be the same signal or the inverse signal. CTM All devices Name 10-bit CTM TM No. 0 TM Input Pin TCK0 TM Output Pin TP0
Compact TM Operation At its core is a 10-bit count-up counter which is driven by a user selectable internal or external clock source. There are also two internal comparators with the names, Comparator A and Comparator P. These comparators will compare the value in the counter with CCRP and CCRA registers. The CCRP is three bits wide whose value is compared with the highest three bits in the counter while the CCRA is the ten bits and therefore compares with all counter bits. The only way of changing the value of the 10-bit counter using the application program, is to clear the counter by changing the TnON bit from low to high. The counter will also be cleared automatically by a counter overflow or a compare match with one of its associated comparators. When these conditions occur, a TM interrupt signal will also usually be generated. The Compact Type TM can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control an output pin. All operating setup conditions are selected using relevant internal registers.
CCRP
3 - b it C o m p a r a to r P
C o m p a ra to r P M a tc h
T n P F In te rru p t
fS
YS
/4
YS
fS
fH /1 6 fH /6 4 fT B C R e s e rv e d TCKn
000 001 010 011 100 101 110 111 TnO N TnPAU
b7~b9
TnO C
1 0 - b it C o u n t- u p C o u n te r
C o u n te r C le a r 0 1
O u tp u t C o n tro l
P o la r ity C o n tro l
TPn
b0~b9
TnC CLR
TnM 1,TnM 0 T n IO 1 , T n IO 0
TnPO L
1 0 - b it C o m p a r a to r A TnC K2~TnC K0 CCRA
C o m p a ra to r A
M a tc h
T n A F In te rru p t
Compact Type TM Block Diagram
Rev. 1.00
55
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
Compact Type TM Register Description Overall operation of the Compact TM is controlled using six registers. A read only register pair exists to store the internal counter 10-bit value, while a read/write register pair exists to store the internal 10-bit CCRA value. The remaining two registers are control registers which setup the different operating and control modes as well as the three CCRP bits. Name TM0C0 TM0C1 TM0DL TM0DH TM0AL TM0AH Bit7 T0PAU T0M1 D7 3/4 D7 3/4 Bit6 T0CK2 T0M0 D6 3/4 D6 3/4 Bit5 T0CK1 T0IO1 D5 3/4 D5 3/4 Bit4 T0CK0 T0IO0 D4 3/4 D4 3/4 Bit3 T0ON T0OC D3 3/4 D3 3/4 Bit2 T0RP2 T0POL D2 3/4 D2 3/4 Bit1 T0RP1 T0DPX D1 D9 D1 D9 Bit0 T0RP0 T0CCLR D0 D8 D0 D8
Compact TM Register List
* TM0DL Register
Bit Name R/W POR Bit 7~0
7 D7 R 0
6 D6 R 0
5 D5 R 0
4 D4 R 0
3 D3 R 0
2 D2 R 0
1 D1 R 0
0 D0 R 0
TM0DL: TM0 Counter Low Byte Register bit 7 ~ bit 0 TM0 10-bit Counter bit 7 ~ bit 0
* TM0DH Register
Bit Name R/W POR Bit 7~2 Bit 1~0
7 3/4 3/4 3/4
6 3/4 3/4 3/4
5 3/4 3/4 3/4
4 3/4 3/4 3/4
3 3/4 3/4 3/4
2 3/4 3/4 3/4
1 D9 R 0
0 D8 R 0
Unimplemented, read as 0 TM0DH: TM0 Counter High Byte Register bit 1 ~ bit 0 TM0 10-bit Counter bit 9 ~ bit 8
* TM0AL Register
Bit Name R/W POR Bit 7~0
7 D7 R/W 0
6 D6 R/W 0
5 D5 R/W 0
4 D4 R/W 0
3 D3 R/W 0
2 D2 R/W 0
1 D1 R/W 0
0 D0 R/W 0
TM0AL: TM0 CCRA Low Byte Register bit 7 ~ bit 0 TM0 10-bit CCRA bit 7 ~ bit 0
Rev. 1.00
56
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
* TM0AH Register
Bit Name R/W POR Bit 7~2 Bit 1~0
7 3/4 3/4 3/4
6 3/4 3/4 3/4
5 3/4 3/4 3/4
4 3/4 3/4 3/4
3 3/4 3/4 3/4
2 3/4 3/4 3/4
1 D9 R/W 0
0 D8 R/W 0
Unimplemented, read as 0 TM0AH: TM0 CCRA High Byte Register bit 1 ~ bit 0 TM0 10-bit CCRA bit 9 ~ bit 8
* TM0C0 Register
Bit Name R/W POR Bit 7
7 T0PAU R/W 0
6 T0CK2 R/W 0
5 T0CK1 R/W 0
4 T0CK0 R/W 0
3 T0ON R/W 0
2 T0RP2 R/W 0
1 T0RP1 R/W 0
0 T0RP0 R/W 0
T0PAU: TM0 Counter Pause Control 0: run 1: pause The counter can be paused by setting this bit high. Clearing the bit to zero restores normal counter operation. When in a Pause condition the TM will remain powered up and continue to consume power. The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. T0CK2~T0CK0: Select TM0 Counter clock 000: fSYS/4 001: fSYS 010: fH/16 011: fH/64 100: fTBC 101: Reserved 110: TCK0 rising edge clock 111: TCK0 falling edge clock These three bits are used to select the clock source for the TM. Selecting the Reserved clock input will effectively disable the internal counter. The external pin clock source can be chosen to be active on the rising or falling edge. The clock source fSYS is the system clock, while fH and fTBC are other internal clocks, the details of which can be found in the oscillator section. T0ON: TM0 Counter On/Off Control 0: Off 1: On This bit controls the overall on/off function of the TM. Setting the bit high enables the counter to run, clearing the bit disables the TM. Clearing this bit to zero will stop the counter from counting and turn off the TM which will reduce its power consumption. When the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value. If the TM is in the Compare Match Output Mode then the TM output pin will be reset to its initial condition, as specified by the T0OC bit, when the T0ON bit changes from low to high. T0RP2~T0RP0: TM0 CCRP 3-bit register, compared with the TM0 Counter bit 9~bit 7 Comparator P Match Period 000: 1024 TM0 clocks 001: 128 TM0 clocks 010: 256 TM0 clocks 011: 384 TM0 clocks 100: 512 TM0 clocks 101: 640 TM0 clocks 110: 768 TM0 clocks 111: 896 TM0 clocks
Bit 6~4
Bit 3
Bit 2~0
Rev. 1.00
57
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
These three bits are used to setup the value on the internal CCRP 3-bit register, which are then compared with the internal counter's highest three bits. The result of this comparison can be selected to clear the internal counter if the T0CCLR bit is set to zero. Setting the T0CCLR bit to zero ensures that a compare match with the CCRP values will reset the internal counter. As the CCRP bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. Clearing all three bits to zero is in effect allowing the counter to overflow at its maximum value.
* TM0C1 Register
Bit Name R/W POR Bit 7~6
7 T0M1 R/W 0
6 T0M0 R/W 0
5 T0IO1 R/W 0
4 T0IO0 R/W 0
3 T0OC R/W 0
2 T0POL R/W 0
1 T0DPX R/W 0
0 T0CCLR R/W 0
T0M1~T0M0: Select TM0 Operating Mode 00: Compare Match Output Mode 01: Undefined Mode 10: PWM Mode 11: Timer/Counter Mode These bits setup the required operating mode for the TM. To ensure reliable operation the TM should be switched off before any changes are made to the T0M1 and T0M0 bits. In the Timer/Counter Mode, the TM output pin control must be disabled. T0IO1~T0IO0: Select TP0 output function Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: Toggle output PWM Mode 00: Force inactive state 01: Force active state 10: PWM output 11: Undefined Timer/counter Mode unused These two bits are used to determine how the TM output pin changes state when a certain condition is reached. The function that these bits select depends upon in which mode the TM is running. In the Compare Match Output Mode, the T0IO1 and T0IO0 bits determine how the TM output pin changes state when a compare match occurs from the Comparator A. The TM output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the Comparator A. When the bits are both zero, then no change will take place on the output. The initial value of the TM output pin should be setup using the T0OC bit in the TM0C1 register. Note that the output level requested by the T0IO1 and T0IO0 bits must be different from the initial value setup using the T0OC bit otherwise no change will occur on the TM output pin when a compare match occurs. After the TM output pin changes state it can be reset to its initial level by changing the level of the T0ON bit from low to high. T0OC: TP0 Output control bit Compare Match Output Mode 0: Initial low 1: Initial high PWM Mode 0: Active low 1: Active high This is the output control bit for the TM output pin. Its operation depends upon whether TM is being used in the Compare Match Output Mode or in the PWM Mode. It has no effect if the TM is in the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of the TM output pin before a compare match occurs. In the PWM Mode it determines if the PWM signal is active high or active low.
Bit 5~4
Bit 3
Rev. 1.00
58
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
Bit 2 T0POL: TP0 Output polarity Control 0: Non-invert 1: Invert This bit controls the polarity of the TP0 output pin. When the bit is set high the TM output pin will be inverted and not inverted when the bit is zero. It has no effect if the TM is in the Timer/Counter Mode. T0DPX: TM0 PWM period/duty Control 0: CCRP - period; CCRA - duty 1: CCRP - duty; CCRA - period This bit, determines which of the CCRA and CCRP registers are used for period and duty control of the PWM waveform. T0CCLR: Select TM0 Counter clear condition 0: TM0 Comparatror P match 1: TM0 Comparatror A match This bit is used to select the method which clears the counter. Remember that the Compact TM contains two comparators, Comparator A and Comparator P, either of which can be selected to clear the internal counter. With the T0CCLR bit set high, the counter will be cleared when a compare match occurs from the Comparator A. When the bit is low, the counter will be cleared when a compare match occurs from the Comparator P or with a counter overflow. A counter overflow clearing method can only be implemented if the CCRP bits are all cleared to zero. The T0CCLR bit is not used in the PWM Mode.
Bit 1
Bit 0
Compact Type TM Operating Modes The Compact Type TM can operate in one of three operating modes, Compare Match Output Mode, PWM Mode or Timer/Counter Mode. The operating mode is selected using the TnM1 and TnM0 bits in the TMnC1 register. Compare Match Output Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register, should be set to 00 respectively. In this mode once the counter is enabled and running it can be cleared by three methods. These are a counter overflow, a compare match from Comparator A and a compare match from Comparator P. When the TnCCLR bit is low, there are two ways in which the counter can be cleared. One is when a compare match occurs from Comparator P, the other is when the CCRP bits are all zero which allows the counter to overflow. Here both TnAF and TnPF interrupt request flags for the Comparator A and Comparator P respectively, will both be generated. If the TnCCLR bit in the TMnC1 register is high then the counter will be cleared when a compare match occurs from Comparator A. However, here only the TnAF interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when TnCCLR is high no TnPF interrupt request flag will be generated. If the CCRA bits are all zero, the counter will overflow when its reaches its maximum 10-bit, 3FF Hex, value, however here the TnAF interrupt request flag will not be generated.
As the name of the mode suggests, after a comparison is made, the TM output pin will change state. The TM output pin condition however only changes state when an TnAF interrupt request flag is generated after a compare match occurs from Comparator A. The TnPF interrupt request flag, generated from a compare match occurs from Comparator P, will have no effect on the TM output pin. The way in which the TM output pin changes state are determined by the condition of the TnIO1 and TnIO0 bits in the TMnC1 register. The TM output pin can be selected using the TnIO1 and TnIO0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from Comparator A. The initial condition of the TM output pin, which is setup after the TnON bit changes from low to high, is setup using the TnOC bit. Note that if the TnIO1 and TnIO0 bits are zero then no pin change will take place. Timer/Counter Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 11 respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the TM output pin is not used. Therefore the above description and Timing Diagrams for the Compare Match Output Mode can be used to understand its function. As the TM output pin is not used in this mode, the pin can be used as a normal I/O pin or other pin-shared function.
Rev. 1.00
59
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
Compare Match Output Mode - TnCCLR = 0 Note: 1. With TnCCLR = 0 the Comparator P match will clear the counter 2. TM output pin controlled only by TnAF flag 3. Output pin reset to initial state by TnON bit rising edge
Rev. 1.00
60
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
Compare Match Output Mode - TnCCLR = 1 Note: 1. With TnCCLR = 1 the Comparator A match will clear the counter 2. TM output pin controlled only by TnAF flag 3.TM output pin reset to initial state by TnON rising edge 4. TnPF flags not generated when TnCCLR = 1
Rev. 1.00
61
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
PWM Output Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 10 respectively. The PWM function within the TM is useful for applications which require functions such as motor control, heating control, illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the TM output pin, a square wave AC waveform can be generated with varying equivalent DC RMS values. As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated waveform is extremely flexible. In the PWM mode, the TnCCLR bit has no effect on the PWM operation. Both of the CCRA and CCRP registers are used to generate the PWM waveform, one register is used to clear the internal counter and thus control the PWM waveform frequency, while the other one is used to control the duty cycle. Which register is used to control either frequency or duty cycle is determined using the TnDPX bit in the TMnC1 register. The PWM waveform frequency and duty cycle can therefore be controlled by the values in the CCRA and CCRP registers. An interrupt flag, one for each of the CCRA and CCRP, will be generated when a compare match occurs from either Comparator A or Comparator P. The TnOC bit in the TMnC1 register is used to select the required polarity of the PWM waveform while the two TnIO1 and TnIO0 bits are used to enable the PWM output or to force the TM output pin to a fixed high or low level. The TnPOL bit is used to reverse the polarity of the PWM output waveform.
PWM Mode - TnDPX = 0 Note: 1. Here TnDPX = 0 - Counter cleared by CCRP 2. Counter Clear sets PWM Period 3. Internal PWM function continues even when TnIO1, TnIO0 = 00 or 01 4. TnCCLR bit has no influence on PWM operation
Rev. 1.00
62
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
PWM Mode - TnDPX = 1 Note: 1. Here TnDPX = 1 - Counter cleared by CCRA 2. Counter Clear sets PWM Period 3. Internal PWM function continues even when TnIO1, TnIO0 = 00 or 01 4. TnCCLR bit has no influence on PWM operation
Rev. 1.00
63
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
Standard Type TM - STM
The Standard Type TM contains five operating modes, which are Compare Match Output, Timer/Event Counter, Capture Input, Single Pulse Output and PWM Output modes. The Standard TM can also be controlled with an external input pin and can drive one or two external output pin. CTM All devices Name 10-bit STM TM No. 1 TM Input Pin TCK1 TM Output Pin TP1
Standard TM Operation At the core is a 10-bit count-up counter which is driven by a user selectable internal or external clock source. There are also two internal comparators with the names, Comparator A and Comparator P. These comparators will compare the value in the counter with CCRP and CCRA registers. The CCRP comparator is 3-bit wide whose value is compared the with highest 3 bits in the counter while the CCRA is the ten bits and therefore compares all counter bits. The only way of changing the value of the 10-bit counter using the application program, is to clear the counter by changing the TnON bit from low to high. The counter will also be cleared automatically by a counter overflow or a compare match with one of its associated comparators. When these conditions occur, a TM interrupt signal will
also usually be generated. The Standard Type TM can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control an output pin. All operating setup conditions are selected using relevant internal registers. Standard Type TM Register Description Overall operation of the Standard TM is controlled using a series of registers. A read only register pair exists to store the internal counter 10-bit value, while a read/write register pair exists to store the internal 10-bit CCRA value. The remaining two registers are control registers which setup the different operating and control modes as well as the three CCRP bits.
CCRP
3 - b it C o m p a r a to r P
C o m p a ra to r P M a tc h
T n P F In te rru p t
fS
YS
/4
YS
fS
fH /1 6 fH /6 4 fT B C R e s e rv e d TCKn
000 001 010 011 100 101 110 111 TnO N TnPAU
b7~b9
TnO C
1 0 - b it C o u n t- u p C o u n te r
C o u n te r C le a r 1 TnC CLR
0
O u tp u t C o n tro l
P o la r ity C o n tro l
TPn
b0~b9
TnM 1,TnM 0 T n IO 1 , T n IO 0
TnPO L
1 0 - b it C o m p a ra to r A TnC K2~TnC K0
C o m p a ra to r A
M a tc h T n IO 1 , T n IO 0
T n A F In te rru p t
CCRA Edge D e te c to r
Standard Type TM Block Diagram
Rev. 1.00
64
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
Name TM1C0 TM1C1 TM1DL TM1DH TM1AL TM1AH Bit7 T1PAU T1M1 D7 3/4 D7 3/4 Bit6 T1CK2 T1M0 D6 3/4 D6 3/4 Bit5 T1CK1 T1IO1 D5 3/4 D5 3/4 Bit4 T1CK0 T1IO0 D4 3/4 D4 3/4 Bit3 T1ON T1OC D3 3/4 D3 3/4 Bit2 T1RP2 T1POL D2 3/4 D2 3/4 Bit1 T1RP1 T1DPX D1 D9 D1 D9 Bit0 T1RP0 T1CCLR D0 D8 D0 D8
Standard TM Register List
* TM1C0 Register
Bit Name R/W POR Bit 7
7 T1PAU R/W 0
6 T1CK2 R/W 0
5 T1CK1 R/W 0
4 T1CK0 R/W 0
3 T1ON R/W 0
2 T1RP2 R/W 0
1 T1RP1 R/W 0
0 T1RP0 R/W 0
T1PAU: TM1 Counter Pause Control 0: run 1: pause The counter can be paused by setting this bit high. Clearing the bit to zero restores normal counter operation. When in a Pause condition the TM will remain powered up and continue to consume power. The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. T1CK2~T1CK0: Select TM1 Counter clock 000: fSYS/4 001: fSYS 010: fH/16 011: fH/64 100: fTBC 101: Reserved 110: TCK1 rising edge clock 111: TCK1 falling edge clock These three bits are used to select the clock source for the TM. Selecting the Reserved clock input will effectively disable the internal counter. The external pin clock source can be chosen to be active on the rising or falling edge. The clock source fSYS is the system clock, while fH and fTBC are other internal clocks, the details of which can be found in the oscillator section. T1ON: TM1 Counter On/Off Control 0: Off 1: On This bit controls the overall on/off function of the TM. Setting the bit high enables the counter to run, clearing the bit disables the TM. Clearing this bit to zero will stop the counter from counting and turn off the TM which will reduce its power consumption. When the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. If the TM is in the Compare Match Output Mode then the TM output pin will be reset to its initial condition, as specified by the T1OC bit, when the T1ON bit changes from low to high.
Bit 6~4
Bit 3
Rev. 1.00
65
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
Bit 2~0 T1RP2~T1RP0: TM1 CCRP 3-bit register, compared with the TM1 Counter bit 9~bit 7 Comparator P Match Period 000: 1024 TM1 clocks 001: 128 TM1 clocks 010: 256 TM1 clocks 011: 384 TM1 clocks 100: 512 TM1 clocks 101: 640 TM1 clocks 110: 768 TM1 clocks 111: 896 TM1 clocks These three bits are used to setup the value on the internal CCRP 3-bit register, which are then compared with the internal counter's highest three bits. The result of this comparison can be selected to clear the internal counter if the T1CCLR bit is set to zero. Setting the T1CCLR bit to zero ensures that a compare match with the CCRP values will reset the internal counter. As the CCRP bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. Clearing all three bits to zero is in effect allowing the counter to overflow at its maximum value.
* TM1C1 Register
Bit Name R/W POR Bit 7~6
7 T1M1 R/W 0
6 T1M0 R/W 0
5 T1IO1 R/W 0
4 T1IO0 R/W 0
3 T1OC R/W 0
2 T1POL R/W 0
1 T1DPX R/W 0
0 T1CCLR R/W 0
T1M1~T1M0: Select TM1 Operating Mode 00: Compare Match Output Mode 01: Capture Input Mode 10: PWM Mode or Single Pulse Output Mode 11: Timer/Counter Mode These bits setup the required operating mode for the TM. To ensure reliable operation the TM should be switched off before any changes are made to the T1M1 and T1M0 bits. In the Timer/Counter Mode, the TM output pin control must be disabled. T1IO1~T1IO0: Select TP1 output function Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: Toggle output PWM Mode/Single Pulse Output Mode 00: Force inactive state 01: Force active state 10: PWM output 11: Single pulse output Capture Input Mode 00: Input capture at rising edge of TP1 01: Input capture at falling edge of TP1 10: Input capture at falling/rising edge of TP1 11: Input capture disabled
Bit 5~4
Rev. 1.00
66
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
Timer/counter Mode: Unused These two bits are used to determine how the TM output pin changes state when a certain condition is reached. The function that these bits select depends upon in which mode the TM is running. In the Compare Match Output Mode, the T1IO1 and T1IO0 bits determine how the TM output pin changes state when a compare match occurs from the Comparator A. The TM output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the Comparator A. When the bits are both zero, then no change will take place on the output. The initial value of the TM output pin should be setup using the T1OC bit in the TM1C1 register. Note that the output level requested by the T1IO1 and T1IO0 bits must be different from the initial value setup using the T1OC bit otherwise no change will occur on the TM output pin when a compare match occurs. After the TM output pin changes state it can be reset to its initial level by changing the level of the T1ON bit from low to high. Bit 3 T1OC: TP1 Output control bit Compare Match Output Mode 0: initial low 1: initial high PWM Mode/ Single Pulse Output Mode 0: Active low 1: Active high This is the output control bit for the TM output pin. Its operation depends upon whether TM is being used in the Compare Match Output Mode or in the PWM Mode/ Single Pulse Output Mode. It has no effect if the TM is in the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of the TM output pin before a compare match occurs. In the PWM Mode it determines if the PWM signal is active high or active low. Bit 2 T1POL: TP1 Output polarity Control 0: non-invert 1: invert This bit controls the polarity of the TP1 output pin. When the bit is set high the TM output pin will be inverted and not inverted when the bit is zero. It has no effect if the TM is in the Timer/Counter Mode. T1DPX: TM1 PWM period/duty Control 0: CCRP - period; CCRA - duty 1: CCRP - duty; CCRA - period This bit, determines which of the CCRA and CCRP registers are used for period and duty control of the PWM waveform. T1CCLR: Select TM1 Counter clear condition 0: TM1 Comparatror P match 1: TM1 Comparatror A match This bit is used to select the method which clears the counter. Remember that the Standard TM contains two comparators, Comparator A and Comparator P, either of which can be selected to clear the internal counter. With the T1CCLR bit set high, the counter will be cleared when a compare match occurs from the Comparator A. When the bit is low, the counter will be cleared when a compare match occurs from the Comparator P or with a counter overflow. A counter overflow clearing method can only be implemented if the CCRP bits are all cleared to zero. The T1CCLR bit is not used in the PWM, Single Pulse or Input Capture Mode.
Bit 1
Bit 0
Rev. 1.00
67
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
TM1DL Register Bit Name R/W POR 7 D7 R 0 6 D6 R 0 5 D5 R 0 4 D4 R 0 3 D3 R 0 2 D2 R 0 1 D1 R 0 0 D0 R 0
Bit 7~0
TM1DL: TM1 Counter Low Byte Register bit 7~bit 0 TM1 10-bit Counter bit 7~bit 0
TM1DH Register Bit Name R/W POR 7 3/4 3/4 3/4 6 3/4 3/4 3/4 5 3/4 3/4 3/4 4 3/4 3/4 3/4 3 3/4 3/4 3/4 2 3/4 3/4 3/4 1 D9 R 0 0 D8 R 0
Bit 7~2 Bit 1~0
Unimplemented, read as 0 TM1DH: TM1 Counter High Byte Register bit 1~bit 0 TM1 10-bit Counter bit 9~bit 8
TM1AL Register Bit Name R/W POR 7 D7 R/W 0 6 D6 R/W 0 5 D5 R/W 0 4 D4 R/W 0 3 D3 R/W 0 2 D2 R/W 0 1 D1 R/W 0 0 D0 R/W 0
Bit 7~0
TM1AL: TM1 CCRA Low Byte Register bit 7~bit 0 TM1 10-bit CCRA bit 7~bit 0
TM1AH Register Bit Name R/W POR 7 3/4 3/4 3/4 6 3/4 3/4 3/4 5 3/4 3/4 3/4 4 3/4 3/4 3/4 3 3/4 3/4 3/4 2 3/4 3/4 3/4 1 D9 R/W 0 0 D8 R/W 0
Bit 7~2 Bit 1~0
Unimplemented, read as 0 TM1AH: TM1 CCRA High Byte Register bit 1~bit 0 TM1 10-bit CCRA bit 9~bit 8
Rev. 1.00
68
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
Standard Type TM Operating Modes The Standard Type TM can operate in one of five operating modes, Compare Match Output Mode, PWM Output Mode, Single Pulse Output Mode, Capture Input Mode or Timer/Counter Mode. The operating mode is selected using the TnM1 and TnM0 bits in the TMnC1 register. Compare Output Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register, should be set to 00 respectively. In this mode once the counter is enabled and running it can be cleared by three methods. These are a counter overflow, a compare match from Comparator A and a compare match from Comparator P. When the TnCCLR bit is low, there are two ways in which the counter can be cleared. One is when a compare match from Comparator P, the other is when the CCRP bits are all zero which allows the counter to overflow. Here both TnAF and TnPF interrupt request flags for Comparator A and Comparator P respectively, will both be generated. If the TnCCLR bit in the TMnC1 register is high then the counter will be cleared when a compare match occurs from Comparator A. However, here only the TnAF interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when TnCCLR is high no TnPF interrupt request flag will be generated. In the Compare Match Output Mode, the CCRA can not be set to 0. As the name of the mode suggests, after a comparison is made, the TM output pin, will change state. The TM output pin condition however only changes state when an TnAF interrupt request flag is generated after a compare match occurs from Comparator A. The TnPF interrupt request flag, generated from a compare match occurs from Comparator P, will have no effect on the TM output pin. The way in which the TM output pin changes state are determined by the condition of the TnIO1 and TnIO0 bits in the TMnC1 register. The TM output pin can be selected using the TnIO1 and TnIO0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from Comparator A. The initial condition of the TM output pin, which is setup after the TnON bit changes from low to high, is setup using the TnOC bit. Note that if the TnIO1 and TnIO0 bits are zero then no pin change will take place.
Compare Match Output Mode - TnCCLR = 0 Note: 1. With TnCCLR = 0 the Comparator P match will clear the counter 2. TM output pin controlled only by TnAF flag 3. Output pin reset to initial state by TnON bit rising edge Rev. 1.00 69 April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
Compare Match Output Mode - TnCCLR = 1 Note: Points to note for above diagram: 1. With TnCCLR = 1 the Comparator A match will clear the counter 2. TM output pin controlled only by TnAF flag 3.TM output pin reset to initial state by TnON rising edge 4. TnPF flags not generated when TnCCLR = 1
Rev. 1.00
70
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
Timer/Counter Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 11 respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the TM output pin is not used. Therefore the above description and Timing Diagrams for the Compare Match Output Mode can be used to understand its function. As the TM output pin is not used in this mode, the pin can be used as a normal I/O pin or other pin-shared function. PWM Output Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 10 respectively and also the TnIO1 and TnIO0 bits should be set to 10 respectively. The PWM function within the TM is useful for applications which require functions such as motor control, heating control, illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the TM output pin, a square wave AC waveform can be generated with varying equivalent DC RMS values. As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated waveform is extremely flexible. In the PWM mode, the TnCCLR bit has no effect as the PWM period. Both of the CCRA and CCRP registers are used to generate the PWM waveform, one register is used to clear the internal counter and thus control the PWM waveform frequency, while the other one is used to control the duty cycle. Which register is used to control either frequency or duty cycle is determined using the TnDPX bit in the TMnC1 register. The PWM waveform frequency and duty cycle can therefore be controlled by the values in the CCRA and CCRP registers. An interrupt flag, one for each of the CCRA and CCRP, will be generated when a compare match occurs from either Comparator A or Comparator P. The TnOC bit in the TMnC1 register is used to select the required polarity of the PWM waveform while the two TnIO1 and TnIO0 bits are used to enable the PWM output or to force the TM output pin to a fixed high or low level. The TnPOL bit is used to reverse the polarity of the PWM output waveform.
PWM Mode - TnDPX = 0 Note: 1. Here TnDPX = 0 - Counter cleared by CCRP 2. Counter Clear sets PWM Period 3. Internal PWM function continues even when TnIO1, TnIO0 = 00 or 01 4. TnCCLR bit has no influence on PWM operation 71 April 16, 2010
Rev. 1.00
HT66F03/HT66F04/HT68F03/HT68F04
PWM Mode - TnDPX = 1 Note: 1. Here TnDPX = 1 - Counter cleared by CCRA 2. Counter Clear sets PWM Period 3. Internal PWM function continues even when TnIO1, TnIO0 = 00 or 01 4. TnCCLR bit has no influence on PWM operation
Rev. 1.00
72
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
Single Pulse Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 10 respectively and also the TnIO1 and TnIO0 bits should be set to 11 respectively. The Single Pulse Output Mode, as the name suggests, will generate a single shot pulse on the TM output pin. The trigger for the pulse output leading edge is a low to high transition of the TnON bit, which can be implemented using the application program. However in the Single Pulse Mode, the TnON bit can also be made to
Com m and S E T "T n O N " or T C K n P in T r a n s itio n S /W L e a d in g E d g e T n O N b it 0(R) 1
automatically change from low to high using the external TCKn pin, which will in turn initiate the Single Pulse output. When the TnON bit transitions to a high level, the counter will start running and the pulse leading edge will be generated. The TnON bit should remain high when the pulse is in its active state. The generated pulse trailing edge will be generated when the TnON bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from Comparator A.
T r a ilin g E d g e T n O N b it 1(R) 0
S /W C o m m a n d C L R "T n O N " or C C R A M a tc h C o m p a re
T M n O u tp u t P in P u ls e W id th = C C R A V a lu e
Single Pulse Generation
Single Pulse Mode Note: 1. Counter stopped by CCRA match 2. CCRP is not used 3. Pulse triggered by TCKn pin or setting TnON bit high 4. TCKn pin active edge will auto set TnON bit 73 April 16, 2010
Rev. 1.00
HT66F03/HT66F04/HT68F03/HT68F04
However a compare match from Comparator A will also automatically clear the TnON bit and thus generate the Single Pulse output trailing edge. In this way the CCRA value can be used to control the pulse width. A compare match from Comparator A will also generate a TM interrupt. The counter can only be reset back to zero when the TnON bit changes from low to high when the counter restarts. In the Single Pulse Mode CCRP is not used. The TnCCLR and TnDPX bits are not used in this Mode. Capture Input Mode To select this mode bits TnM1 and TnM0 in the TMnC1 register should be set to 01 respectively. This mode enables the external signal to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements. The external signal is supplied on the TP1 pin, whose active edge can be either a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the TnIO1 and TnIO0 bits in the TMnC1 register. The counter is started when the TnON bit changes from low to high which is initiated using the application program. When the required edge transition appears on the TP1 pin, the present value in the counter will be latched into the CCRA registers and a TM interrupt generated. Irrespective of what events occur on the TP1 pin the counter will continue to free run until the TnON bit changes from high to low. When a CCRP compare match occurs the counter will reset back to zero; in this way the CCRP value can be used to control the maximum counter value. When a CCRP compare match occurs from Comparator P, a TM interrupt will also be generated. Counting the number of overflow interrupt signals from the CCRP can be a useful method in measuring long pulse widths. The TnIO1 and TnIO0 bits can select the active trigger edge on the TP1 pin to be a rising edge, falling edge or both edge types. If the TnIO1 and TnIO0 bits are both set high, then no capture operation will take place irrespective of what happens on the TP1 pin, however it must be noted that the counter will continue to run. As the TP1 pin is pin shared with other functions, care must be taken if the TM is in the Input Capture Mode. This is because if the pin is setup as an output, then any transitions on this pin may cause an input capture operation to be executed. The TnCCLR and TnDPX bits are not used in this Mode.
Counter Value CCRP YY XX
TnM1, TnM0 = 01
Counter overflow
Stop Counter Reset
Pause Resume
Time
TnON bit
TnPAU bit Active edge Active edge Active edges
TM Capture Pin CCRA Int. Flag TnAF CCRP Int. Flag TnPF
CCRA Value TnIO1, TnIO0 Value
XX
YY
XX
YY
00 - Rising edge
01 - Falling edge
10 - Both edges
11 - Disable Capture
Capture Input Mode Note: 1. TnM1, TnM0 = 01 and active edge set by TnIO1 and TnIO0 bits 2. TM Capture input pin active edge transfers counter value to CCRA 3. TnCCLR bit not used 4. No output function - TnOC and TnPOL bits not used 5. CCRP sets counter maximum value
Rev. 1.00
74
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
Enhanced Type TM - ETM
The Enhanced Type TM contains five operating modes, which are Compare Match Output, Timer/Event Counter, Capture Input, Single Pulse Output and PWM Output modes. The Enhanced TM can also be controlled with an external input pin and can drive three or two external output pins. CTM HT66F03/HT68F03/HT68F04 HT66F04 Name 3/4 10-bit ETM TM No. 3/4 2 TM Input Pin 3/4 TCK2 TM Output Pin 3/4 TP2A, TP2B
Enhanced TM Operation At its core is a 10-bit count-up/count-down counter which is driven by a user selectable internal or external clock source. There are three internal comparators with the names, Comparator A, Comparator B and Comparator P. These comparators will compare the value in the counter with the CCRA, CCRB and CCRP registers. The CCRP comparator is 3-bits wide whose value is compared with the highest 3-bits in the counter while CCRA and CCRB are 10-bits wide and therefore compared with all counter bits.
The only way of changing the value of the 10-bit counter using the application program, is to clear the counter by changing the TnON bit from low to high. The counter will also be cleared automatically by a counter overflow or a compare match with one of its associated comparators. When these conditions occur, a TM interrupt signal will also usually be generated. The Enhanced Type TM can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control output pins. All operating setup conditions are selected using relevant internal registers.
CCRP C o m p a ra to r P M a tc h
3 - b it C o m p a r a to r P
T n P F In te rru p t
fS
YS
/4
YS
fS
fH /1 6 fH /6 4 fT B C R e s e rv e d TCKn
000 001 010 011 100 101 110 111
b7~b9
TnAO C
1 0 - b it U p /D o w n C o u n te r
C o u n te r C le a r 0 1 TnC CLR
O u tp u t C o n tro l
P o la r ity C o n tro l
TPnA
TnO N TnPAU
b0~b9
TnAM 1,TnAM 0 T n A IO 1 , T n A IO 0
TnAPO L
TnC K2~TnC K0
1 0 - b it C o m p a ra to r A
C o m p a ra to r A
M a tc h
TnAF In te rru p t
T n A IO 1 , T n A IO 0 CCRA Edge D e te c to r TnBO C
1 0 - b it C o m p a ra to r B
C o m p a ra to r B
M a tc h TnBF In te rru p t Edge D e te c to r
O u tp u t C o n tro l
P o la r ity C o n tro l
TPnB
CCRB
TnBM 1,TnBM 0 T n B IO 1 , T n B IO 0
TnBPO L
T n IO 1 , T n IO 0
Enhanced Type TM Block Diagram
Rev. 1.00
75
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
Enhanced Type TM Register Description Overall operation of the Enhanced TM is controlled using a series of registers. A read only register pair exists to store the internal counter 10-bit value, while two read/write register pairs exist to store the internal 10-bit CCRA and CCRB value. The remaining three registers are control registers which setup the different operating and control modes as well as the three CCRP bits. Name TM2C0 TM2C1 TM2C2 TM2DL TM2DH TM2AL TM2AH TM2BL TM2BH Bit7 T2PAU T2AM1 T2BM1 D7 3/4 D7 3/4 D7 3/4 Bit6 T2CK2 T2AM0 T2BM0 D6 3/4 D6 3/4 D6 3/4 Bit5 T2CK1 T2AIO1 T2BIO1 D5 3/4 D5 3/4 D5 3/4 Bit4 T2CK0 T2AIO0 T2BIO0 D4 3/4 D4 3/4 D4 3/4 Bit3 T2ON T2AOC T2BOC D3 3/4 D3 3/4 D3 3/4 Bit2 T2RP2 T2APOL T2BPOL D2 3/4 D2 3/4 D2 3/4 Bit1 T2RP1 T2CDN T2PWM1 D1 D9 D1 D9 D1 D9 Bit0 T2RP0 T2CCLR T2PWM0 D0 D8 D0 D8 D0 D8
10-bit Enhanced TM Register List
* 10-bit Enhanced TM Register List - HT66F04
TM2C0 Register Bit Name R/W POR 7 T2PAU R/W 0 6 T2CK2 R/W 0 5 T2CK1 R/W 0 4 T2CK0 R/W 0 3 T2ON R/W 0 2 T2RP2 R/W 0 1 T2RP1 R/W 0 0 T2RP0 R/W 0
Bit 7
T2PAU: TM2 Counter Pause Control 0: run 1: pause The counter can be paused by setting this bit high. Clearing the bit to zero restores normal counter operation. When in a Pause condition the TM will remain powered up and continue to consume power. The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again.
Bit 6~4
T2CK2~T2CK0: Select TM2 Counter clock 000: fSYS/4 001: fSYS 010: fH/16 011: fH/64 100: fTBC 101: Reserved 110: TCK2 rising edge clock 111: TCK2 falling edge clock These three bits are used to select the clock source for the TM. Selecting the Reserved clock input will effectively disable the internal counter. The external pin clock source can be chosen to be active on the rising or falling edge. The clock source fSYS is the system clock, while fH and fTBC are other internal clocks, the details of which can be found in the oscillator section.
Bit 3
T2ON: TM2 Counter On/Off Control 0: Off 1: On This bit controls the overall on/off function of the TM. Setting the bit high enables the counter to run, clearing the bit disables the TM. Clearing this bit to zero will stop the counter from counting and turn off the TM which will reduce its power consumption. When the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again.
Rev. 1.00
76
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
If the TM is in the Compare Match Output Mode then the TM output pin will be reset to its initial condition, as specified by the T2AOC or T2BOC bit, when the T2ON bit changes from low to high. Bit 2~0 T2RP2~T2RP0: TM2 CCRP 3-bit register, compared with the TM2 Counter bit 9~bit 7 Comparator P Match Period 000: 1024 TM2 clocks 001: 128 TM2 clocks 010: 256 TM2 clocks 011: 384 TM2 clocks 100: 512 TM2 clocks 101: 640 TM2 clocks 110: 768 TM2 clocks 111: 896 TM2 clocks These three bits are used to setup the value on the internal CCRP 3-bit register, which are then compared with the internal counters highest three bits. The result of this comparison can be selected to clear the internal counter if the T2CCLR bit is set to zero. Setting the T2CCLR bit to zero ensures that a compare match with the CCRP values will reset the internal counter. As the CCRP bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. Clearing all three bits to zero is in effect allowing the counter to overflow at its maximum value.
TM2C1 Register Bit Name R/W POR 7 T2AM1 R/W 0 6 T2AM0 R/W 0 5 T2AIO1 R/W 0 4 T2AIO0 R/W 0 3 T2AOC R/W 0 2 T2APOL R/W 0 1 T2CDN R 0 0 T2CCLR R/W 0
Bit 7~6
T2AM1~T2AM0: Select TM2 CCRA Operating Mode 00: Compare Match Output Mode 01: Capture Input Mode 10: PWM Mode or Single Pulse Output Mode 11: Timer/Counter Mode These bits setup the required operating mode for the TM. To ensure reliable operation the TM should be switched off before any changes are made to the T2AM1 and T2AM0 bits. In the Timer/Counter Mode, the TM output pin control must be disabled.
Bit 5~4
T2AIO1~T2AIO0: Select TP2A output function Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: Toggle output PWM Mode/ Single Pulse Output Mode 00: Force inactive state 01: Force active state 10: PWM output 11: Single pulse output Capture Input Mode 00: Input capture at rising edge of TP2A 01: Input capture at falling edge of TP2A 10: Input capture at falling/rising edge of TP2A 11: Input capture disabled Timer/counter Mode Unused These two bits are used to determine how the TM output pin changes state when a certain condition is reached. The function that these bits select depends upon in which mode the TM is running.
Rev. 1.00
77
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
In the Compare Match Output Mode, the T2AIO1 and T2AIO0 bits determine how the TM output pin changes state when a compare match occurs from the Comparator A. The TM output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the Comparator A. When the bits are both zero, then no change will take place on the output. The initial value of the TM output pin should be setup using the T2AOC bit in the TM2C1 register. Note that the output level requested by the T2AIO1 and T2AIO0 bits must be different from the initial value setup using the T2AOC bit otherwise no change will occur on the TM output pin when a compare match occurs. After the TM output pin changes state, it can be reset to its initial level by changing the level of the T2ON bit from low to high. Bit 3 T2AOC: TP2A Output control bit Compare Match Output Mode 0: Initial low 1: Initial high PWM Mode/ Single Pulse Output Mode 0: Active low 1: Active high This is the output control bit for the TM output pin. Its operation depends upon whether TM is being used in the Compare Match Output Mode or in the PWM Mode/ Single Pulse Output Mode. It has no effect if the TM is in the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of the TM output pin before a compare match occurs. In the PWM Mode it determines if the PWM signal is active high or active low. Bit 2 T2APOL: TP2A Output polarity Control 0: Non-invert 1: Invert This bit controls the polarity of the TP2A output pin. When the bit is set high the TM output pin will be inverted and not inverted when the bit is zero. It has no effect if the TM is in the Timer/Counter Mode. Bit 1 T2CDN: TM2 Counter count up or down flag 0: Count up 1: Count down T2CCLR: Select TM2 Counter clear condition 0: TM2 Comparator P match 1: TM2 Comparator A match This bit is used to select the method which clears the counter. Remember that the Enhanced TM contains two comparators, Comparator A and Comparator P, either of which can be selected to clear the internal counter. With the T2CCLR bit set high, the counter will be cleared when a compare match occurs from the Comparator A. When the bit is low, the counter will be cleared when a compare match occurs from the Comparator P or with a counter overflow. A counter overflow clearing method can only be implemented if the CCRP bits are all cleared to zero. The T2CCLR bit is not used in the PWM, Single Pulse or Input Capture Mode.
Bit 0
Rev. 1.00
78
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
TM2C2 Register Bit Name R/W POR 7 T2BM1 R/W 0 6 T2BM0 R/W 0 5 T2BIO1 R/W 0 4 T2BIO0 R/W 0 3 T2BOC R/W 0 2 T2BPOL R/W 0 1 T2PWM1 R/W 0 0 T2PWM0 R/W 0
Bit 7~6
T2BM1~T2BM0: Select TM2 CCRB Operating Mode 00: Compare Match Output Mode 01: Capture Input Mode 10: PWM Mode or Single Pulse Output Mode 11: Timer/Counter mode These bits setup the required operating mode for the TM. To ensure reliable operation the TM should be switched off before any changes are made to the T2BM1 and T2BM0 bits. In the Timer/Counter Mode, the TM output pin control must be disabled.
Bit 5~4
T2BIO1~T2BIO0: Select TP2B output function Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: Toggle output PWM Mode/Single Pulse Output Mode 00: Force inactive state 01: Force active state 10: PWM output 11: Single pulse output Capture Input Mode 00: Input capture at rising edge of TP2B 01: Input capture at falling edge of TP2B 10: Input capture at falling/rising edge of TP2B 11: Input capture disabled Timer/counter Mode Unused These two bits are used to determine how the TM output pin changes state when a certain condition is reached. The function that these bits select depends upon in which mode the TM is running. In the Compare Match Output Mode, the T2BIO1 and T2BIO0 bits determine how the TM output pin changes state when a compare match occurs from the Comparator A. The TM output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the Comparator A. When the bits are both zero, then no change will take place on the output. The initial value of the TM output pin should be setup using the T2BOC bit in the TM2C2 register. Note that the output level requested by the T2BIO1 and T2BIO0 bits must be different from the initial value setup using the T2BOC bit otherwise no change will occur on the TM output pin when a compare match occurs. After the TM output pin changes state it can be reset to its initial level by changing the level of the T2ON bit from low to high.
Bit 3
T2BOC: TP2B Output control bit Compare Match Output Mode 0: Initial low 1: Initial high PWM Mode/ Single Pulse Output Mode 0: Active low 1: Active high This is the output control bit for the TM output pin. Its operation depends upon whether TM is being used in the Compare Match Output Mode or in the PWM Mode/ Single Pulse Output Mode. It has no effect if the TM is in the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of the TM output pin before a compare match occurs. In the PWM Mode it determines if the PWM signal is active high or active low.
Rev. 1.00
79
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
Bit 2 T2BPOL: TP2B Output polarity Control 0: Non-invert 1: Invert This bit controls the polarity of the TP2B output pin. When the bit is set high the TM output pin will be inverted and not inverted when the bit is zero. It has no effect if the TM is in the Timer/Counter Mode. Bit 1~0 T2PWM1~T2PWM0: Select PWM Mode 00: Edge aligned 01: Centre aligned, compare match on count up 10: Centre aligned, compare match on count down 11: Centre aligned, compare match on count up or down
TM2DL Register Bit Name R/W POR 7 D7 R 0 6 D6 R 0 5 D5 R 0 4 D4 R 0 3 D3 R 0 2 D2 R 0 1 D1 R 0 0 D0 R 0
Bit 7~0
TM2DL: TM2 Counter Low Byte Register bit 7~bit 0 TM2 10-bit Counter bit 7~bit 0
TM2DH Register Bit Name R/W POR 7 3/4 3/4 3/4 6 3/4 3/4 3/4 5 3/4 3/4 3/4 4 3/4 3/4 3/4 3 3/4 3/4 3/4 2 3/4 3/4 3/4 1 D9 R 0 0 D8 R 0
Bit 7~2 Bit 1~0
Unimplemented, read as 0 TM2DH: TM2 Counter High Byte Register bit 1~bit 0 TM2 10-bit Counter bit 9~bit 8
TM2AL Register Bit Name R/W POR 7 D7 R/W 0 6 D6 R/W 0 5 D5 R/W 0 4 D4 R/W 0 3 D3 R/W 0 2 D2 R/W 0 1 D1 R/W 0 0 D0 R/W 0
Bit 7~0
TM2AL: TM2 CCRA Low Byte Register bit 7~bit 0 TM2 10-bit CCRA bit 7~bit 0
TM2AH Register Bit Name R/W POR 7 3/4 3/4 3/4 6 3/4 3/4 3/4 5 3/4 3/4 3/4 4 3/4 3/4 3/4 3 3/4 3/4 3/4 2 3/4 3/4 3/4 1 D9 R/W 0 0 D8 R/W 0
Bit 7~2 Bit 1~0
Unimplemented, read as 0 TM2AH: TM2 CCRA High Byte Register bit 1~bit 0 TM210-bit CCRA bit 9~bit 8
Rev. 1.00
80
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
TM2BL Register Bit Name R/W POR 7 D7 R/W 0 6 D6 R/W 0 5 D5 R/W 0 4 D4 R/W 0 3 D3 R/W 0 2 D2 R/W 0 1 D1 R/W 0 0 D0 R/W 0
Bit 7 ~ 0
TM2BL: TM2 CCRB Low Byte Register bit 7~bit 0 TM2 10-bit CCRB bit 7~bit 0
TM2BH Register Bit Name R/W POR 7 3/4 3/4 3/4 6 3/4 3/4 3/4 5 3/4 3/4 3/4 4 3/4 3/4 3/4 3 3/4 3/4 3/4 2 3/4 3/4 3/4 1 D9 R/W 0 0 D8 R/W 0
Bit 7~2 Bit 1~0
Unimplemented, read as 0 TM2BH: TM2 CCRB High Byte Register bit 1~bit 0 TM2 10-bit CCRB bit 9 ~ bit 8
Enhanced Type TM Operating Modes The Enhanced Type TM can operate in one of five operating modes, Compare Match Output Mode, PWM Output Mode, Single Pulse Output Mode, Capture Input Mode or Timer/Counter Mode. The operating mode is selected using the TnAM1 and TnAM0 bits in the TMnC1, and the TnBM1 and TnBM0 bits in the TMnC2 register.
CCRA Compare Match Output Mode CCRA Timer/Counter Mode CCRA PWM Output Mode CCRA Single Pulse Output Mode CCRA Input Capture Mode
ETM Operating Mode
CCRB Compare Match Output Mode CCRB Timer/Counter Mode CCRB PWM Output Mode CCRB Single Pulse Output Mode CCRB Input Capture Mode
O O O 3/4 O
O O O 3/4 O
O O O 3/4 O
3/4 3/4 3/4 O 3/4
3/4 3/4 3/4 3/4 O
Note: O allowed to be used. 3/4: not allowed to be used
Compare Output Mode To select this mode, bits TnAM1, TnAM0 and TnBM1, TnBM0 in the TMnC1/TMnC2 registers should be all cleared to zero. In this mode once the counter is enabled and running it can be cleared by three methods. These are a counter overflow, a compare match from Comparator A and a compare match from Comparator P. When the TnCCLR bit is low, there are two ways in which the counter can be cleared. One is when a compare match occurs from Comparator P, the other is when the CCRP bits are all zero which allows the counter to overflow. Here both the TnAF and TnPF interrupt request flags for Comparator A and Comparator P respectively, will both be generated.
If the TnCCLR bit in the TMnC1 register is high then the counter will be cleared when a compare match occurs from Comparator A. However, here only the TnAF interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when TnCCLR is high no TnPF interrupt request flag will be generated.
Rev. 1.00
81
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
As the name of the mode suggests, after a comparison is made, the TM output pin, will change state. The TM output pin condition however only changes state when an TnAF or TnBF interrupt request flag is generated after a compare match occurs from Comparator A or Comparator B. The TnPF interrupt request flag, generated from a compare match from Comparator P, will have no effect on the TM output pin. The way in which the TM output pin changes state is determined by the condition of the TnAIO1 and TnAIO0 bits in the TMnC1 register for ETM CCRA, and the TnBIO1 and TnBIO0 bits in the TMnC2 register for ETM CCRB. The TM output pin can be selected using the TnAIO1, TnAIO0 bits (for the TPnA pin) and TnBIO1, TnBIO0 bits (for the TPnB pins) to go high, to go low or to toggle from its present condition when a compare match occurs from Comparator A or a compare match occurs from Comparator B. The initial condition of the TM output pin, which is setup after the TnON bit changes from low to high, is setup using the TnAOC or TnBOC bit for TPnA or TPnB output pin. Note that if the TnAIO1,TnAIO0 and TnBIO1, TnBIO0 bits are zero then no pin change will take place.
ETM CCRA Compare Match Output Mode - TnCCLR = 0 Note: 1. With TnCCLR = 0 the Comparator P match will clear the counter 2. TPnA output pin controlled only by TnAF flag 3. Output pin reset to initial state by TnON bit rising edge
Rev. 1.00
82
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
ETM CCRB Compare Match Output Mode - TnCCLR = 0 Note: 1. With TnCCLR = 0 the Comparator P match will clear the counter 2. TPnB output pin controlled only by TnBF flag 3. Output pin reset to initial state by TnON bit rising edge
Rev. 1.00
83
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
ETM CCRA Compare Match Output Mode - TnCCLR = 1 Note: 1. With TnCCLR = 1 the Comparator A match will clear the counter 2. TPnA output pin controlled only by TnAF flag 3. TPnA output pin reset to initial state by TnON rising edge 4. TnPF flags not generated when TnCCLR = 1
Rev. 1.00
84
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
ETM CCRB Compare Match Output Mode - TnCCLR = 1 Note: 1. With TnCCLR = 1 the Comparator A match will clear the counter 2. TPnB output pin controlled only by TnBF flag 3. TPnB output pin reset to initial state by TnON rising edge 4. TnPF flags not generated when TnCCLR = 1
Rev. 1.00
85
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
Timer/Counter Mode To select this mode, bits TnAM1, TnAM0 and TnBM1, TnBM0 in the TMnC1 and TMnC2 register should all be set high. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the TM output pin is not used. Therefore the above description and Timing Diagrams for the Compare Match Output Mode can be used to understand its function. As the TM output pin is not used in this mode, the pin can be used as a normal I/O pin or other pin-shared function. PWM Output Mode To select this mode, the required bit pairs, TnAM1, TnAM0 and TnBM1, TnBM0 should be set to 10 respectively and also the TnAIO1, TnAIO0 and TnBIO1, TnBIO0 bits should be set to 10 respectively. The PWM function within the TM is useful for applications which require functions such as motor control, heating control, illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the TM output pin, a square wave AC waveform can be generated with varying equivalent DC RMS values. As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated waveform is extremely flexible. In the PWM mode, the TnCCLR bit is used to determine in which way the PWM period is controlled. With the TnCCLR bit set high, the PWM period
* ETM, PWM Mode, Edge-aligned Mode, TnCCLR=0
can be finely controlled using the CCRA registers. In this case the CCRB registers are used to set the PWM duty value (for TPnB output pin). The CCRP bits are not used and TPnA output pin is not used. The PWM output can only be generated on the TPnB output pin. With the TnCCLR bit cleared to zero, the PWM period is set using one of the eight values of the three CCRP bits, in multiples of 128. Now both CCRA and CCRB registers can be used to setup different duty cycle values to provide dual PWM outputs on their relative TPnA and TPnB pins. The TnPWM1 and TnPWM0 bits determine the PWM alignment type, which can be either edge or centre type. In edge alignment, the leading edge of the PWM signals will all be generated concurrently when the counter is reset to zero. With all power currents switching on at the same time, this may give rise to problems in higher power applications. In centre alignment the centre of the PWM active signals will occur sequentially, thus reducing the level of simultaneous power switching currents. Interrupt flags, one for each of the CCRA, CCRB and CCRP, will be generated when a compare match occurs from either the Comparator A, Comparator B or Comparator P. The TnAOC and TnBOC bits in the TMnC1 and TMnC2 register are used to select the required polarity of the PWM waveform while the two TnAIO1, TnAIO0 and TnBIO1, TnBIO0 bits pairs are used to enable the PWM output or to force the TM output pin to a fixed high or low level. The TnAPOL and TnBPOL bit are used to reverse the polarity of the PWM output waveform.
CCRP Period A Duty B Duty
001b 128
010b 256
011b 384
100b 512 CCRA CCRB
101b 640
110b 768
111b 896
000b 1024
* ETM, PWM Mode, Edge-aligned Mode, TnCCLR=1
CCRA Period B Duty
1 1
2 2
3 3
511 511 CCRB
512 512
1021 1021
1022 1022
1023 1023
* ETM, PWM Mode, Center-aligned Mode, TnCCLR=0
CCRP Period A Duty B Duty
001b 256
010b 512
011b 768
100b 1024
101b 1280
110b 1536
111b 1792
000b 2046
(CCRA2)-1 (CCRB2)-1
* ETM, PWM Mode, Center-aligned Mode, TnCCLR=1
CCRA Period B Duty
1 2
2 4
3 6
511 1022
512 1024
1021 2042
1022 2044
1023 2046
(CCRB2)-1
Rev. 1.00
86
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
PWM Mode - Edge Aligned Note: 1. Here TnCCLR = 0 therefore CCRP clears counter and determines PWM period 2. Internal PWM function continues even when TnAIO1, TnAIO0 ( or TnBIO1, TnBIO0) = 00 or 01 3. CCRA controls TPnA PWM duty and CCRB controls TPnB PWM duty
Rev. 1.00
87
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
PWM Mode - Edge Aligned Note: 1. Here TnCCLR = 1 therefore CCRA clears counter and determines PWM period 2. Internal PWM function continues even when TnBIO1, TnBIO0 = 00 or 01 3. CCRA controls TPnB PWM period and CCRB controls TPnB PWM duty
Rev. 1.00
88
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
PWM Mode - Centre Aligned Note: 1. Here TnCCLR = 0 therefore CCRP clears counter and determines PWM period 2. TnPWM1/TnPWM0 = 11 therefore PWM is centre aligned 3. Internal PWM function continues even when TnAIO1, TnAIO0 ( or TnBIO1, TnBIO0) = 00 or 01 4. CCRA controls TPnA PWM duty and CCRB controls TPnB PWM duty 5. CCRP will generate an interrupt request when the counter decrements to its zero value.
Rev. 1.00
89
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
PWM Mode - Centre Aligned Note: 1. Here TnCCLR = 1 therefore CCRA clears counter and determines PWM period 2. TnPWM1/TnPWM0 = 11 therefore PWM is centre aligned 3. Internal PWM function continues even when TnBIO1, TnBIO0 = 00 or 01 4. CCRA controls the TPnB PWM period and CCRB controls the TPnB PWM duty 5. CCRP will generate an interrupt request when the counter decrements to its zero value.
Rev. 1.00
90
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
Single Pulse Output Mode To select this mode, the required bit pairs, TnAM1, TnAM0 and TnBM1, TnBM0 should be set to 10 respectively and also the corresponding TnAIO1, TnAIO0 and TnBIO1, TnBIO0 bits should be set to 11 respectively. The Single Pulse Output Mode, as the name suggests, will generate a single shot pulse on the TM output pin. The trigger for the pulse TPnA output leading edge is a low to high transition of the TnON bit, which can be implemented using the application program. The trigger for the pulse TPnB output leading edge is a compare match from Comparator B, which can be implemented using the application program. However in the Single Pulse Mode, the TnON bit can also be made to automatically change from low to high using the external TCKn pin, which will in turn initiate the Single Pulse output of TPnA. When the TnON bit transitions to a high level, the counter will start running and the pulse leading edge of TPnA will be generated. The TnON bit should remain high when the pulse is in its active state. The generated pulse trailing edge of TPnA and TPnB will be generated when the TnON bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from Comparator A. However a compare match from Comparator A will also automatically clear the TnON bit and thus generate the Single Pulse output trailing edge of TPnA and TPnB. In this way the CCRA value can be used to control the pulse width of TPnA. The CCRA-CCRB value can be used to control the pulse width of TPnB. A compare match from Comparator A and Comparator B will also generate TM interrupts. The counter can only be reset back to zero when the TnON bit changes from low to high when the counter restarts. In the Single Pulse Mode CCRP is not used. The TnCCLR bit is also not used.
Com m and S E T "T n O N " or T C K n P in T r a n s itio n
S /W
L e a d in g E d g e T n O N b it 0(R) 1
T r a ilin g E d g e T n O N b it 1(R) 0
S /W C o m m a n d C L R "T n O N " or C C R A M a tc h C o m p a re
T P n A O u tp u t P in P u ls e W id th = C C R A V a lu e T P n B O u tp u t P in P u ls e W id th = C C R A - C C R B V a lu e
Single Pulse Generation
Rev. 1.00
91
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
Counter Value CCRA
Pause Resume Counter Stops by software Counter reset when TnON returns high
Counter Stopped by CCRA
TnAM1, TnAM0 and TnBM1, TnBM0 = 10; TnAIO1, TnAIO0 and TnBIO1, TnBIO0 = 11
CCRB
Time TnON bit
Auto. s et by TCKn pin Software Trigger Cleared by CCRA match Software Trigger Software Clear Software Trigger
TCKn pin
TCKn pin Trigger
TnPAU bit TnAPOL, TnBPOL bit CCRB Int. Flag TnBF CCRA Int. Flag TnAF
TnAIO1, TnAIO0 and TnBIO1, TnBIO0 = 11 Single Pulse Output TnAIO1, TnAIO0 and TnBIO1, TnBIO0 = 00 Output Inactive TnAIO1, TnAIO0 and TnBIO1, TnBIO0 = 11
TPnA Pin TnAOC = 1 TPnA Pin TnAOC = 0
Pulse Width set by CCRA Here TnAIO1, TnAIO0 and TnBIO1, TnBIO0 = 00 Output Forced to Inactive level but counter keeps running internally TnAIO1, TnAIO0 and TnBIO1, TnBIO0 = 11 Resume Single Pulse Output Output Inverts When TnAPOL = 1
TPnB Pin TnBOC = 1
Pulse Width set by CCRA - CCRB
TPnB Pin TnBOC = 0
Output Inverts When TnBPOL = 1
ETM - Single Pulse Mode
Rev. 1.00
92
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
Capture Input Mode To select this mode bits TnAM1, TnAM0 and TnBM1, TnBM0 in the TMnC1 and TMnC2 registers should be set to 01 respectively. This mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements. The external signal is supplied on the TPnA and TPnB pins, whose active edge can be either a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the TnAIO1, TnAIO0 and TnBIO1, TnBIO0 bits in the TMnC1 and TMnC2 registers. The counter is started when the TnON bit changes from low to high which is initiated using the application program. When the required edge transition appears on the TPnA and TPnB pins the present value in the counter will be latched into the CCRA and CCRB registers and a TM interrupt generated. Irrespective of what events occur on the TPnA and TPnB pins the counter will continue to free run until the TnON bit changes from high to low. When a CCRP compare match occurs the counter will reset back to zero; in this way the CCRP value can be used to control the maximum counter value. When a CCRP compare match occurs from Comparator P, a TM interrupt will also be generated. Counting the number of overflow interrupt signals from the CCRP can be a useful method in measuring long pulse widths. The TnAIO1, TnAIO0 and TnBIO1, TnBIO0 bits can select the active trigger edge on the TPnA and TPnB pins to be a rising edge, falling edge or both edge types. If the TnAIO1, TnAIO0 and TnBIO1, TnBIO0 bits are both set high, then no capture operation will take place irrespective of what happens on the TPnA and TPnB pins, however it must be noted that the counter will continue to run. As the TPnA and TPnB pins are pin shared with other functions, care must be taken if the TM is in the Capture Input Mode. This is because if the pin is setup as an output, then any transitions on this pin may cause an input capture operation to be executed. The TnCCLR, TnAOC, TnBOC, TnAPOL and TnBPOL bits are not used in this mode.
TnAM1, TnAM0 = 01
Counter Value CCRP YY XX
Pause Resume
Counter overflow
Stop Counter Reset
Time
TnON bit
TnPAU bit Active edge Active edge Active edges
TM Capture Pin CCRA Int. Flag TnAF CCRP Int. Flag TnPF
CCRA Value TnAIO1, TnAIO0 Value
XX
YY
XX
YY
00 - Rising edge
01 - Falling edge
10 - Both edges
11 - Disable Capture
ETM CCRA Capture Input Mode Note: 1. TnAM1, TnAM0 = 01 and active edge set by TnAIO1 and TnAIO0 bits 2. TM Capture input pin active edge transfers counter value to CCRA 3. TnCCLR bit not used 4. No output function - TnAOC and TnAPOL bits not used 5. CCRP sets counter maximum value
Rev. 1.00
93
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
TnBM1, TnBM0 = 01
Counter Value CCRP YY XX
Pause Resume
Counter overflow
Stop Counter Reset
Time
TnON bit
TnPAU bit Active edge Active edge Active edges
TM Capture Pin CCRB Int. Flag TnBF CCRP Int. Flag TnPF
CCRB Value TnBIO1, TnBIO0 Value
XX
YY
XX
YY
00 - Rising edge
01 - Falling edge
10 - Both edges
11 - Disable Capture
ETM CCRB Capture Input Mode Note: 1. TnBM1, TnBM0 = 01 and active edge set by TnBIO1 and TnBIO0 bits 2. TM Capture input pin active edge transfers counter value to CCRB 3. TnCCLR bit not used 4. No output function - TnBOC and TnBPOL bits not used 5. CCRP sets counter maximum value
Rev. 1.00
94
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
Analog to Digital Converter
The need to interface to real world analog signals is a common requirement for many electronic systems. However, to properly process these signals by a microcontroller, they must first be converted into digital signals by A/D converters. By integrating the A/D conversion electronic circuitry into the microcontroller, the need for external components is reduced significantly with the corresponding follow-on benefits of lower costs and reduced component space requirements. A/D Overview The devices contains a multi-channel analog to digital converter which can directly interface to external analog signals, such as that from sensors or other control signals and convert these signals directly into either a 12-bit digital value. Input Channels 4 A/D Channel Select Bits ACS4, ACS1~ACS0 Input Pins AN0~AN3
Part No. HT66F03 HT66F04
The accompanying block diagram shows the overall internal structure of the A/D converter, together with its associated registers. A/D Converter Register Description Overall operation of the A/D converter is controlled using six registers. A read only register pair exists to store the ADC data 12-bit value. The remaining three or four registers are control registers which setup the operating and control function of the A/D converter.
Register Name ADRL(ADRFS=0) ADRL(ADRFS=1) ADRH(ADRFS=0) ADRH(ADRFS=1) ADCR0 ADCR1 ACERL
Bit 7 D3 D7 D11 3/4 START ACS4 3/4 6 D2 D6 D10 3/4 EOCB V125EN 3/4 5 D1 D5 D9 3/4 ADOFF 3/4 3/4 4 D0 D4 D8 3/4 ADRFS VREFS 3/4 3 3/4 D3 D7 D11 3/4 3/4 ACE3 2 3/4 D2 D6 D10 3/4 ADCK2 ACE2 1 3/4 D1 D5 D9 ACS1 ADCK1 ACE1 0 3/4 D0 D4 D8 ACS0 ADCK0 ACE0
HT66F03/HT66F04 A/D Converter Register List A/D Converter Data Registers - ADRL, ADRH As the devices contain an internal 12-bit A/D converter, they require two data registers to store the converted value. These are a high byte register, known as ADRH, and a low byte register, known as ADRL. After the conversion process takes place, these registers can be directly read by the microcontroller to obtain the digitised conversion value. As only 12 bits of the 16-bit register space is utilised, the format in which the data is stored is controlled by the ADRFS bit in the ADCR0 register as shown in the accompanying table. D0~D11 are the A/D conversion result data bits. Any unused bits will be read as zero. ADRFS 0 1 ADRH 7 D11 0 6 D10 0 5 D9 0 4 D8 0 3 D7 D11 2 D6 D10 1 D5 D9 0 D4 D8 7 D3 D7 6 D2 D6 5 D1 D5 ADRL 4 D0 D4 3 0 D3 2 0 D2 1 0 D1 0 0 D0
A/D Data Registers
Rev. 1.00
95
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
A/D Converter Control Registers ADCR0, ADCR1, ACERL To control the function and operation of the A/D converter, three control registers known as ADCR0, ADCR1 and ACERL are provided. These 8-bit registers define functions such as the selection of which analog channel is connected to the internal A/D converter, the digitised data format, the A/D clock source as well as controlling the start function and monitoring the A/D converter end of conversion status. The ACS1~ACS0 bits in the ADCR0 register and ACS4 bit is the ADCR1 register define the ADC input channel number. As the device contains only one actual analog to digital converter hardware circuit, each of the individual 4 analog inputs must be routed to the converter. It is the function of the ACS4, ACS1 and ACS0 bits to determine which analog channel input pins or internal 1.25V is actually connected to the internal A/D converter. The ACERL control register contains the ACER3~ ACER0 bits which determine which pins on Port A are used as analog inputs for the A/D converter input and which pins are not to be used as the A/D converter input. Setting the corresponding bit high will select the A/D input function, clearing the bit to zero will select either the I/O or other pin-shared function. When the pin is selected to be an A/D input, its original function whether it is an I/O or other pin-shared function will be removed. In addition, any internal pull-high resistors connected to these pins will be automatically removed if the pin is selected to be an A/D input.
fS AD CK2~ADCK0 AC E3~ACE0 A /D 2
YS
V
DD
N
(N = 0 ~ 6 )
P B 1 /V R E F ADOFF B it A /D VREFS B it R e fe r e n c e V o lta g e ADRL ADRH V
SS
C lo c k
PA3 PA2 PA1 PA0
/A N /A N /A N /A N 2 1 0
3 A /D C o n v e rte r
A /D D a ta R e g is te r s
1 .2 5 V V125EN AC S4, AC S1~ACS0 START EOCB ADOFF
ADRFS b it
A/D Converter Structure
Rev. 1.00
96
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
* ADCR0 Register
HT66F03/HT66F04 Bit Name R/W POR 7 START R/W 0 6 EOCB R 1 5 ADOFF R/W 1 4 ADRFS R/W 0 3 3/4 3/4 3/4 2 3/4 3/4 3/4 1 ACS1 R/W 0 0 ACS0 R/W 0
Bit 7
START: Start the A/D conversion 0(R)1(R)0 : start 0(R)1 : reset the A/D converter and set EOCB to 1 This bit is used to initiate an A/D conversion process. The bit is normally low but if set high and then cleared low again, the A/D converter will initiate a conversion process. When the bit is set high the A/D converter will be reset.
Bit 6
EOCB: End of A/D conversion flag 0: A/D conversion ended 1: A/D conversion in progress This read only flag is used to indicate when an A/D conversion process has completed. When the conversion process is running the bit will be high.
Bit 5
ADOFF : ADC module power on/off control bit 0: ADC module power on 1: ADC module power off This bit controls the power to the A/D internal function. This bit should be cleared to zero to enable the A/D converter. If the bit is set high then the A/D converter will be switched off reducing the device power consumption. As the A/D converter will consume a limited amount of power, even when not executing a conversion, this may be an important consideration in power sensitive battery powered applications. Note: 1. it is recommended to set ADOFF=1 before entering IDLE/SLEEP Mode for saving power. 2. ADOFF=1 will power down the ADC module.
Bit 4
ADRFS: ADC Data Format Control 0: ADC Data MSB is ADRH bit 7, LSB is ADRL bit 4 1: ADC Data MSB is ADRH bit 3, LSB is ADRL bit 0 This bit controls the format of the 12-bit converted A/D value in the two A/D data registers. Details are provided in the A/D data register section.
Bit 3~2 Bit 1~0
unimplemented, read as 0 ACS1, ACS0: Select A/D channel (when ACS4 is 0) 00: AN0 01: AN1 10: AN2 11: AN3 These are the A/D channel select control bits. As there is only one internal hardware A/D converter each of the four A/D inputs must be routed to the internal converter using these bits. If bit ACS4 in the ADCR1 register is set high, then the internal 1.25V reference voltage source will be routed to the A/D Converter.
Rev. 1.00
97
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
* ADCR1 Register
HT66F03/HT66F04 Bit Name R/W POR 7 ACS4 R/W 0 6 V125EN R/W 0 5 3/4 3/4 3/4 4 VREFS R/W 0 3 3/4 3/4 3/4 2 ADCK2 R/W 0 1 ADCK1 R/W 0 0 ADCK0 R/W 0
Bit 7
ACS4: Selecte Internal 1.25V as ADC input Control 0: Disable 1: Enable This bit enables 1.25V to be connected to the A/D converter. The V125EN bit must first have been set to enable the bandgap circuit 1.25V voltage to be used by the A/D converter. When the ACS4 bit is set high, the bandgap 1.25V voltage will be routed to the A/D converter and the other A/D input channels disconnected.
Bit 6
V125EN: Internal 1.25V Control 0: Disable 1: Enable This bit controls the internal Bandgap circuit on/off function to the A/D converter. When the bit is set high the bandgap voltage 1.25V can be used by the A/D converter. If 1.25V is not used by the A/D converter and the LVR/LVD function is disabled then the bandgap reference circuit will be automatically switched off to conserve power. When 1.25V is switched on for use by the A/D converter, a time tBG should be allowed for the bandgap circuit to stabilise before implementing an A/D conversion.
Bit 5 Bit 4
unimplemented, read as 0 VREFS: Selecte ADC reference voltage 0: Internal ADC power 1: VREF pin This bit is used to select the reference voltage for the A/D converter. If the bit is high, then the A/D converter reference voltage is supplied on the external VREF pin. If the pin is low, then the internal reference is used which is taken from the power supply pin VDD. When the A/D converter reference voltage is supplied on the external VREF pin which is pin-shared with other functions, all of the pin-shared functions except VREF on this pin are disabled.
Bit 3 Bit 2~0
unimplemented, read as 0 ADCK2, ADCK1, ADCK0: Select ADC clock source 000: fSYS 001: fSYS/2 010: fSYS/4 011: fSYS/8 100: fSYS/16 101: fSYS/32 110: fSYS/64 111: Undefined These three bits are used to select the clock source for the A/D converter.
Rev. 1.00
98
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
* ACERL Register
HT66F03/HT66F04 Bit Name R/W POR 7 3/4 3/4 3/4 6 3/4 3/4 3/4 5 3/4 3/4 3/4 4 3/4 3/4 3/4 3 ACE3 R/W 1 2 ACE2 R/W 1 1 ACE1 R/W 1 0 ACE0 R/W 1
Bit 7~4 Bit 3
unimplemented, read as 0 ACE3: Define PA3 is A/D input or not 0: Not A/D input 1: A/D input, AN3 ACE2: Define PA2 is A/D input or not 0: Not A/D input 1: A/D input, AN2 ACE1: Define PA1 is A/D input or not 0: Not A/D input 1: A/D input, AN1 ACE0: Define PA0 is A/D input or not 0: Not A/D input 1: A/D input, AN0
Bit 2
Bit 1
Bit 0
A/D Operation The START bit in the ADCR0 register is used to start and reset the A/D converter. When the microcontroller sets this bit from low to high and then low again, an analog to digital conversion cycle will be initiated. When the START bit is brought from low to high but not low again, the EOCB bit in the ADCR0 register will be set high and the analog to digital converter will be reset. It is the START bit that is used to control the overall start operation of the internal analog to digital converter. The EOCB bit in the ADCR0 register is used to indicate when the analog to digital conversion process is complete. This bit will be automatically set to 0 by the microcontroller after a conversion cycle has ended. In addition, the corresponding A/D interrupt request flag will be set in the interrupt control register, and if the interrupts are enabled, an appropriate internal interrupt signal will be generated. This A/D internal interrupt signal will direct the program flow to the associated A/D internal interrupt address for processing. If the A/D internal interrupt is disabled, the microcontroller can be used to poll the EOCB bit in the ADCR0 register to check whether it has been cleared as an alternative method of detecting the end of an A/D conversion cycle.
The clock source for the A/D converter, which originates from the system clock fSYS, can be chosen to be either fSYS or a subdivided version of fSYS. The division ratio value is determined by the ADCK2~ADCK0 bits in the ADCR1 register. Although the A/D clock source is determined by the system clock fSYS, and by bits ADCK2~ADCK0, there are some limitations on the maximum A/D clock source speed that can be selected. As the minimum value of permissible A/D clock period, tADCK, is 0.5ms, care must be taken for system clock frequencies equal to or greater than 4MHz. For example, if the system clock operates at a frequency of 4MHz, the ADCK2~ADCK0 bits should not be set to 000. Doing so will give A/D clock periods that are less than the minimum A/D clock period which may result in inaccurate A/D conversion values. Refer to the following table for examples, where values marked with an asterisk * show where, depending upon the device, special care must be taken, as the values may be less than the specified minimum A/D Clock Period.
Rev. 1.00
99
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
A/D Clock Period (tADCK) fSYS ADCK2, ADCK1, ADCK0 = 000 (fSYS) 1ms 500ns 250ns* 125ns* 83ns* ADCK2, ADCK1, ADCK0 = 001 (fSYS/2) 2ms 1ms 500ns 250ns* 167ns* ADCK2, ADCK1, ADCK0 = 010 (fSYS/4) 4ms 2ms 1ms 500ns 333ns* ADCK2, ADCK1, ADCK0 = 011 (fSYS/8) 8ms 4ms 2ms 1ms 667ns ADCK2, ADCK1, ADCK0 = 100 (fSYS/16) 16ms 8ms 4ms 2ms 1.33ms ADCK2, ADCK1, ADCK0 = 101 (fSYS/32) 32ms 16ms 8ms 4ms 2.67ms ADCK2, ADCK1, ADCK0 = 110 (fSYS/64) 64ms 32ms 16ms 8ms 5.33ms ADCK2, ADCK1, ADCK0 = 111 Undefined Undefined Undefined Undefined Undefined
1MHz 2MHz 4MHz 8MHz 12MHz
A/D Clock Period Examples
Controlling the power on/off function of the A/D converter circuitry is implemented using the ADOFF bit in the ADCR0 register. This bit must be zero to power on the A/D converter. When the ADOFF bit is cleared to zero to power on the A/D converter internal circuitry a certain delay, as indicated in the timing diagram, must be allowed before an A/D conversion is initiated. Even if no pins are selected for use as A/D inputs by clearing the ACE3~ACE0 bits in the ACERH registers, if the ADOFF bit is zero then some power will still be consumed. In power conscious applications it is therefore recommended that the ADOFF is set high to reduce power consumption when the A/D converter function is not being used. The reference voltage supply to the A/D Converter can be supplied from either the positive power supply pin, VDD, or from an external reference sources supplied on pin VREF. The desired selection is made using the VREFS bit. As the VREF pin is pin-shared with other functions, when the VREFS bit is set high, the VREF pin function will be selected and the other pin functions will be disabled automatically. A/D Input Pins All of the A/D analog input pins are pin-shared with the I/O pins on Port A as well as other functions. The ACE3~ ACE0 bits in the ACERL register, determine whether the input pins are setup as A/D converter analog inputs or whether they have other functions. If the ACE3~ACE0 bits for its corresponding pin is set high then the pin will be setup to be an A/D converter input and the original pin functions disabled. In this way, pins can be changed under program control to change their function between A/D inputs and other functions. All pull-high resistors, which are setup through register programming, will be automatically disconnected if the pins are setup as A/D inputs. Note that it is not necessary to first setup the A/D pin as an input in the PAC port control register to enable the A/D input as when the ACE3~ACE0 bits enable an A/D input, the status of the port control register will be overridden. Rev. 1.00 100
The A/D converter has its own reference voltage pin, VREF, however the reference voltage can also be supplied from the power supply pin, a choice which is made through the VREFS bit in the ADCR1 register. The analog input values must not be allowed to exceed the value of VREF.
P A 0 /A N 0 AC S4,AC S1~AC S0 In p u t V o lta g e B u ffe r V125EN P A 3 /A N 3 1 .2 5 V
1 2 - b it A D C
VREFS VDD
Bandgap R e fe re n c e V o lta g e
V
REF
P A 1 /V R E F
A/D Input Structure Summary of A/D Conversion Steps The following summarises the individual steps that should be executed in order to implement an A/D conversion process.
* Step 1
Select the required A/D conversion clock by correctly programming bits ADCK2~ADCK0 in the ADCR1 register.
* Step 2
Enable the A/D by clearing the ADOFF bit in the ADCR0 register to zero.
* Step 3
Select which channel is to be connected to the internal A/D converter by correctly programming the ACS4, ACS1 and ACS0 bits which are also contained in the ADCR1 and ADCR0 register.
* Step 4
Select which pins are to be used as A/D inputs and configure them by correctly programming the ACE3~ACE0 bits in the ACERH register.
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
* Step 5
If the interrupts are to be used, the interrupt control registers must be correctly configured to ensure the A/D converter interrupt function is active. The master interrupt control bit, EMI, and the A/D converter interrupt bit, EADI, must both be set high to do this.
* Step 6
The power-on reset condition of the A/D converter control registers will ensure that the shared function pins are setup as A/D converter inputs. If any of the A/D converter input pins are to be used for functions, then the A/D converter control register bits must be properly setup to disable the A/D input configuration. A/D Transfer Function As the devices contain a 12-bit A/D converter, its full-scale converted digitised value is equal to FFFH. Since the full-scale analog input value is equal to the VDD or VREF voltage, this gives a single bit analog input value of VDD or VREF divided by 4096. 1 LSB= (VDD or VREF) 4096 The A/D Converter input voltage value can be calculated using the following equation: A/D input voltage = A/D output digital value (VDD or VREF) 4096 The diagram shows the ideal transfer function between the analog input value and the digitised output value for the A/D converter. Except for the digitised zero value, the subsequent digitised values will change at a point 0.5 LSB below where they would change without the offset, and the last full scale digitised value will change at a point 1.5 LSB below the VDD or VREF level. A/D Programming Example The following two programming examples illustrate how to setup and implement an A/D conversion. In the first example, the method of polling the EOCB bit in the ADCR0 register is used to detect when the conversion cycle is complete, whereas in the second example, the A/D interrupt is used to determine when the conversion is complete.
The analog to digital conversion process can now be initialised by setting the START bit in the ADCR register from low to high and then low again. Note that this bit should have been originally cleared to zero.
* Step 7
To check when the analog to digital conversion process is complete, the EOCB bit in the ADCR0 register can be polled. The conversion process is complete when this bit goes low. When this occurs the A/D data registers ADRL and ADRH can be read to obtain the conversion value. As an alternative method, if the interrupts are enabled and the stack is not full, the program can wait for an A/D interrupt to occur. Note: When checking for the end of the conversion process, if the method of polling the EOCB bit in the ADCR0 register is used, the interrupt enable step above can be omitted. The accompanying diagram shows graphically the various stages involved in an analog to digital conversion process and its associated timing. After an A/D conversion process has been initiated by the application program, the microcontroller internal hardware will begin to carry out the conversion, during which time the program can continue with other functions. The time taken for the A/D conversion is 16tADCK where tADCK is equal to the A/D clock period. Programming Considerations During microcontroller operations where the A/D converter is not being used, the A/D internal circuitry can be switched off to reduce power consumption, by setting bit ADOFF high in the ADCR0 register. When this happens, the internal A/D converter circuits will not consume power irrespective of what analog voltage is applied to their input lines. If the A/D converter input lines are used as normal I/Os, then care must be taken as if the input voltage is not at a valid logic level, then this may lead to some increase in power consumption.
Rev. 1.00
101
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
ADOFF tO ADC M o d u le ON o ff on
N2ST
A /D tA
DS
s a m p lin g tim e
A /D tA
DS
s a m p lin g tim e
o ff
on
START
EOCB
AC S4,AC S1, ACS0
011B P o w e r-o n R eset R e s e t A /D c o n v e rte r 1 : D e fin e p o r t c o n fig u r a tio n 2 : S e le c t a n a lo g c h a n n e l A /D
010B S ta rt o f A /D c o n v e r s io n
000B S ta rt o f A /D c o n v e r s io n R e s e t A /D c o n v e rte r E n d o f A /D c o n v e r s io n
001B S ta rt o f A /D c o n v e r s io n R e s e t A /D c o n v e rte r E n d o f A /D c o n v e r s io n
tA D C c o n v e r s io n tim e
A /D
tA D C c o n v e r s io n tim e
A/D Conversion Timing
1 .5 L S B FFFH FFEH FFDH A /D C o n v e r s io n R e s u lt 03H 02H 01H 0 1 2 3 4093 4094 4095 4096 ( V
DD
0 .5 L S B
orV 4096
REF
)
A n a lo g In p u t V o lta g e
Ideal A/D Transfer Function
Rev. 1.00
102
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
Example: using an EOCB polling method to detect the end of conversion clr ADE ; disable ADC interrupt mov a,03H mov ADCR1,a ; select fSYS/8 as A/D clock and switch off 1.25V clr ADOFF mov a,0Fh ; setup ACERL to configure pins AN0~AN3 mov ACERL,a mov a,00h mov ADCR0,a ; enable and connect AN0 channel to A/D converter : start_conversion: clr START ; high pulse on start bit to initiate conversion set START ; reset A/D clr START ; start A/D polling_EOC: sz EOCB ; poll the ADCR0 register EOCB bit to detect end ; of A/D conversion jmp polling_EOC ; continue polling mov a,ADRL ; read low byte conversion result value mov ADRL_buffer,a ; save result to user defined register mov a,ADRH ; read high byte conversion result value mov ADRH_buffer,a ; save result to user defined register : : jmp start_conversion ; start next a/d conversion Example: using the interrupt method to detect the end of conversion clr ADE ; disable ADC interrupt mov a,03H mov ADCR1,a ; select fSYS/8 as A/D clock and switch off 1.25V Clr ADOFF mov a,0Fh ; setup ACERL to configure pins AN0~AN3 mov ACERL,a mov a,00h mov ACERH,00h ; ACERH is only for HT66F60 mov a,00h mov ADCR0,a ; enable and connect AN0 channel to A/D converter Start_conversion: clr START ; high pulse on START bit to initiate conversion set START ; reset A/D clr START ; start A/D clr ADF ; clear ADC interrupt request flag set ADE ; enable ADC interrupt set EMI ; enable global interrupt : : ; ADC interrupt service routine ADC_ISR: mov acc_stack,a ; save ACC to user defined memory mov a,STATUS mov status_stack,a ; save STATUS to user defined memory : : mov a,ADRL ; read low byte conversion result value mov adrl_buffer,a ; save result to user defined register mov a,ADRH ; read high byte conversion result value mov adrh_buffer,a ; save result to user defined register : : EXIT_INT_ISR: mov a,status_stack mov STATUS,a ; restore STATUS from user defined memory mov a,acc_stack ; restore ACC from user defined memory reti
Rev. 1.00
103
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
Comparators
An analog comparator is contained within these devices. These functions offer flexibility via their register controlled features such as power-down, polarity select, hysteresis etc. In sharing their pins with normal I/O pins the comparators do not waste precious I/O pins if there functions are otherwise unused.
CPOL C+ CCSEL COUT CX
Comparator Interrupt The comparator possesses its own interrupt function. When the comparator output changes state, its relevant interrupt flag will be set, and if the corresponding interrupt enable bit is set, then a jump to its relevant interrupt vector will be executed. Note that it is the changing state of the COUT bit and not the output pin which generates an interrupt. If the microcontroller is in the SLEEP or IDLE Mode and the Comparator is enabled, then if the external input lines cause the Comparator output to change state, the resulting generated interrupt flag will also generate a wake-up. If it is required to disable a wake-up from occurring, then the interrupt flag should be first set high before entering the SLEEP or IDLE Mode. Programming Considerations If the comparator is enabled, it will remain active when the microcontroller enters the SLEEP or IDLE Mode, however as it will consume a certain amount of power, the user may wish to consider disabling it before the SLEEP or IDLE Mode is entered. As comparator pins are shared with normal I/O pins the I/O registers for these pins will be read as zero (port control register is 1) or read as port data register value (port control register is 0) if the comparator function is enabled.
Comparator Comparator Operation The device contains a comparator function which is used to compare two analog voltages and provide an output based on their difference. Full control over the internal comparators is provided via the control register CPC assigned to the comparator. The comparator output is recorded via a bit in the control register, but can also be transferred out onto a shared I/O pin. Additional comparator functions include, output polarity, hysteresis functions and power down control. Any pull-high resistors connected to the shared comparator input pins will be automatically disconnected when the comparator is enabled. As the comparator inputs approach their switching level, some spurious output signals may be generated on the comparator output due to the slow rising or falling nature of the input signals. This can be minimised by selecting the hysteresis function will apply a small amount of positive feedback to the comparator. Ideally the comparator should switch at the point where the positive and negative inputs signals are at the same voltage level, however, unavoidable input offsets introduce some uncertainties here. The hysteresis function, if enabled, also increases the switching offset value.
Rev. 1.00
104
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
* CPC Register
Bit Name R/W POR Bit 7
7 CSEL R/W 1
6 CEN R/W 0
5 CPOL R/W 0
4 COUT R 0
3 COS R/W 0
2 3/4 3/4 3/4
1 3/4 3/4 3/4
0 CHYEN R/W 1
CSEL: Select Comparator pins or I/O pins 0: I/O pin select 1: Comparator pin select This is the Comparator pin or I/O pin select bit. If the bit is high the comparator will be selected and the two comparator input pins will be enabled. As a result, these two pins will lose their I/O pin functions. Any pull-high configuration options associated with the comparator shared pins will also be automatically disconnected.
Bit 6
CEN: Comparator On/Off control 0: Off 1: On This is the Comparator on/off control bit. If the bit is zero the comparator will be switched off and no power consumed even if analog voltages are applied to its inputs. For power sensitive applications this bit should be cleared to zero if the comparator is not used or before the device enters the SLEEP or IDLE mode.
Bit 5
CPOL: Comparator output polarity 0: output not inverted 1: output inverted This is the comparator polarity bit. If the bit is zero then the COUT bit will reflect the non-inverted output condition of the comparator. If the bit is high the comparator COUT bit will be inverted.
Bit 4
COUT: Comparator output bit CPOL=0 0: C+ < C1: C+ > CCPOL=1 0: C+ > C1: C+ < CThis bit stores the comparator output bit. The polarity of the bit is determined by the voltages on the comparator inputs and by the condition of the CPOL bit.
Bit 3
CS: Output path select 0: CX pin 1: Internal use This is the comparator output path select control bit. If the bit is set to 0 and the CSEL bit is 1 the comparator output is connected to an external CX pin. If the bit is set to 1 or the CSEL bit is 0 the comparator output signal is only used internally by the device allowing the shared comparator output pin to retain its normal I/O operation.
Bit 2~1 Bit 0
unimplemented, read as 0 CHYEN: Hysteresis Control 0: Off 1: On This is the hysteresis control bit and if set high will apply a limited amount of hysteresis to the comparator, as specified in the Comparator Electrical Characteristics table. The positive feedback induced by hysteresis reduces the effect of spurious switching near the comparator threshold.
Rev. 1.00
105
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
Interrupts
Interrupts are an important part of any microcontroller system. When an external event or an internal function such as a Timer Module or an A/D converter requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. The device contains several external interrupt and internal interrupts functions. The external interrupt is generated by the action of the external INT pin, while the internal interrupts are generated by various internal functions such as the TMs, Comparator, Time Base, LVD, EEPROM, SIM and the A/D converter. Interrupt Registers Overall interrupt control, which basically means the setting of request flags when certain microcontroller conditions occur and the setting of interrupt enable bits by the application program, is controlled by a series of registers, located in the Special Purpose Data Memory, as shown in the accompanying table. The number of registers depends upon the device chosen but fall into three categories. The first is the INTC0~INTC2 registers which setup the primary interrupts, the second is the MFI0~MFI2 registers which setup the Multi-function interrupts. Finally there is an INTEG register to setup the external interrupt trigger edge type. Each register contains a number of enable bits to enable or disable individual registers as well as interrupt flags to indicate the presence of an interrupt request. The naming convention of these follows a specific pattern. First is listed an abbreviated interrupt type, then the (optional) number of that interrupt followed by either an E for enable/disable bit or F for request flag. Function Global INT Pin Comparator A/D Converter Multi-function Time Base LVD EEPROM Enable Bit EMI INTE CPE ADE MFnE TBnE LVE DEE TnPE TM TnAE TnBE Request Flag 3/4 INTF CPF ADF MFnF TBnF LVF DEF TnPF n=0~2 TnAF TnBF n=2 Notes 3/4 3/4 3/4 3/4 n=0~2 n=0~1 3/4 3/4
Interrupt Register Bit Naming Conventions
* Interrupt Register Contents
HT66F03 Bit Name 7 INTEG INTC0 INTC1 INTC2 MFI0 MFI1* MFI2 3/4 3/4 DEF 3/4 3/4 TB0F 3/4 T1AF 6 3/4 MF0F ADF 3/4 T1PF 5 3/4 CPF MF2F 3/4 T0AF 4 3/4 INTF 3/4 TB1F T0PF MF0E TB0E 3/4 T1AE CPE ADE 3/4 T1PE 3 2 1 INTS1 INTE MF2E 3/4 T0AE 0 INTS0 EMI 3/4 TB1E T0PE
Reserved LVF 3/4 3/4 DEE LVE
* MFI1 register is reserved for advanced expansion. It is recommended that do not access the MFI1 register and keep its initial setting to avoid malfunction.
Rev. 1.00
106
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
HT66F04 Bit Name 7 INTEG INTC0 INTC1 INTC2 MFI0 MFI1 MFI2 3/4 3/4 3/4 TB0F 3/4 T1AF 6 3/4 MF0F ADF 3/4 T1PF T2BF 3/4 5 3/4 CPF MF2F 3/4 T0AF T2AF DEF 4 3/4 INTF MF1F TB1F T0PF T2PF LVF MF0E TB0E 3/4 T1AE 3/4 3/4 CPE ADE 3/4 T1PE T2BE 3/4 3 2 1 INTS1 INTE MF2E 3/4 T0AE T2AE DEE 0 INTS0 EMI MF1E TB1E T0PE T2PE LVE
HT68F03/HT68F04 Bit Name 7 INTEG INTC0 INTC1 INTC2 MFI0 MFI1* MFI2 3/4 3/4 DEF 3/4 3/4 TB0F 3/4 T1AF 6 3/4 MF0F 3/4 3/4 T1PF 5 3/4 CPF MF2F 3/4 T0AF 4 3/4 INTF 3/4 TB1F T0PF MF0E TB0E 3/4 T1AE CPE 3/4 3/4 T1PE 3 2 1 INTS1 INTE MF2E 3/4 T0AE 0 INTS0 EMI 3/4 TB1E T0PE
Reserved LVF 3/4 3/4 DEE LVE
* MFI1 register is reserved for advanced expansion. It is recommended that do not access the MFI1 register and keep its initial setting to avoid malfunction.
* INTEG Register
Bit Name R/W POR Bit 7~2 Bit 1~0
7 3/4 3/4 3/4
6 3/4 3/4 3/4
5 3/4 3/4 3/4
4 3/4 3/4 3/4
3 3/4 3/4 3/4
2 3/4 3/4 3/4
1 INTS1 R/W 1
0 INTS0 R/W 1
unimplemented, read as 0 INTS1, INTS0: interrupt edge control for INT pin 00: disable 01: rising edge 10: falling edge 11: rising and falling edges
Rev. 1.00
107
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
* INTC0 Register
Bit Name R/W POR Bit 7 Bit 6
7 3/4 3/4 3/4
6 MF0F R/W 0
5 CPF R/W 0
4 INTF R/W 0
3 MF0E R/W 0
2 CPE R/W 0
1 INTE R/W 0
0 EMI R/W 0
unimplemented, read as 0 MF0F: Multi-function Interrupt 0 Request Flag 0: no request 1: interrupt request CPF: Comparator interrupt request flag 0: no request 1: interrupt request INTF: INT pin interrupt request flag 0: no request 1: interrupt request MF0E: Multi-function Interrupt 0 Control 0: disable 1: enable CPE: Comparator interrupt control 0: disable 1: enable INTE: INT interrupt control 0: disable 1: enable EMI: Global interrupt control 0: disable 1: enable
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
* INTC1 Register
HT66F03 Bit Name R/W POR 7 TB0F R/W 0 6 ADF R/W 0 5 MF2F R/W 0 4 3/4 3/4 3/4 3 TB0E R/W 0 2 ADE R/W 0 1 MF2E R/W 0 0 3/4 3/4 3/4
Bit 7
Bit 6
TB0F: Time Base 0 Interrupt Request Flag 0: no request 1: interrupt request ADF: A/D Converter Interrupt Request Flag 0: no request 1: interrupt request MF2F: Multi-function Interrupt 2 Request Flag 0: no request 1: interrupt request reserved and can not be used, read as 0 TB0E: Time Base 0 Interrupt Control 0: disable 1: enable ADE: A/D converter interrupt control 0: disable 1: enable MF2E: Multi-function Interrupt 2 Control 0: disable 1: enable reserved and can not be used, read as 0 108 April 16, 2010
Bit 5
Bit 4 Bit 3
Bit 2
Bit 1
Bit 0
Rev. 1.00
HT66F03/HT66F04/HT68F03/HT68F04
HT66F04 Bit Name R/W POR 7 TB0F R/W 0 6 ADF R/W 0 5 MF2F R/W 0 4 MF1F R/W 0 3 TB0E R/W 0 2 ADE R/W 0 1 MF2E R/W 0 0 MF1E R/W 0
Bit 7
Bit 6
TB0F: Time Base 0 Interrupt Request Flag 0: no request 1: interrupt request ADF: A/D Converter Interrupt Request Flag 0: no request 1: interrupt request MF2F: Multi-function Interrupt 2 Request Flag 0: no request 1: interrupt request MF1F: Multi-function Interrupt 1 Request Flag 0: no request 1: interrupt request TB0E: Time Base 0 Interrupt Control 0: disable 1: enable ADE: A/D converter interrupt control 0: disable 1: enable MF2E: Multi-function Interrupt 2 Control 0: disable 1: enable MF1E: Multi-function Interrupt Control 0: disable 1: enable
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
HT68F03/HT68F04 Bit Name R/W POR 7 TB0F R/W 0 6 3/4 3/4 3/4 5 MF2F R/W 0 4 3/4 3/4 3/4 3 TB0E R/W 0 2 3/4 3/4 3/4 1 MF2E R/W 0 0 3/4 3/4 3/4
Bit 7
TB0F: Time Base 0 Interrupt Request Flag 0: no request 1: interrupt request unimplemented, read as 0 MF2F: Multi-function Interrupt 2 Request Flag 0: no request 1: interrupt request reserved and can not be used, read as 0 TB0E: Time Base 0 Interrupt Control 0: disable 1: enable unimplemented, read as 0 MF2E: Multi-function Interrupt 2 Control 0: disable 1: enable reserved and can not be used, read as 0
Bit 6 Bit 5
Bit 4 Bit 3
Bit 2 Bit 1
Bit 0
Rev. 1.00
109
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
* INTC2 Register
Bit Name R/W POR Bit 7~5 Bit 4
7 3/4 3/4 3/4
6 3/4 3/4 3/4
5 3/4 3/4 3/4
4 TB1F R/W 0
3 3/4 3/4 3/4
2 3/4 3/4 3/4
1 3/4 3/4 3/4
0 TB1E R/W 0
unimplemented, read as 0 TB1F: Time Base 1 Interrupt Request Flag 0: no request 1: interrupt request unimplemented, read as 0 TB1E: Time Base 1 Interrupt Control 0: disable 1: enable
Bit 3~1 Bit 0
* MFI0 Register
Bit Name R/W POR Bit 7
7 T1AF R/W 0
6 T1PF R/W 0
5 T0AF R/W 0
4 T0PF R/W 0
3 T1AE R/W 0
2 T1PE R/W 0
1 T0AE R/W 0
0 T0PE R/W 0
T1AF: TM1 Comparator A match interrupt request flag 0: no request 1: interrupt request T1PF: TM1 Comparator P match interrupt request flag 0: no request 1: interrupt request T0AF: TM0 Comparator A match interrupt request flag 0: no request 1: interrupt request T0PF: TM0 Comparator P match interrupt request flag 0: no request 1: interrupt request T1AE: TM1 Comparator A match interrupt control 0: disable 1: enable T1PE: TM1 Comparator P match interrupt control 0: disable 1: enable T0AE: TM0 Comparator A match interrupt control 0: disable 1: enable T0PE: TM0 Comparator P match interrupt control 0: disable 1: enable
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Rev. 1.00
110
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
* MFI1 Register
HT66F04 Bit Name R/W POR 7 3/4 3/4 3/4 6 T2BF R/W 0 5 T2AF R/W 0 4 T2PF R/W 0 3 3/4 3/4 3/4 2 T2BE R/W 0 1 T2AE R/W 0 0 T2PE R/W 0
Bit 7 Bit 6
unimplemented, read as 0 T2BF: TM2 Comparator B match interrupt request flag 0: no request 1: interrupt request T2AF: TM2 Comparator A match interrupt request flag 0: no request 1: interrupt request T2PF: TM2 Comparator B match interrupt request flag 0: no request 1: interrupt request unimplemented, read as 0 T2BE: TM2 Comparator P match interrupt control 0: disable 1: enable T2AE: TM2 Comparator A match interrupt control 0: disable 1: enable T2PE: TM2 Comparator P match interrupt control 0: disable 1: enable
Bit 5
Bit 4
Bit 3 Bit 2
Bit 1
Bit 0
* MFI2 Register
Bit Name R/W POR Bit 7~6 Bit 5
7 3/4 3/4 3/4
6 3/4 3/4 3/4
5 DEF R/W 0
4 LVF R/W 0
3 3/4 3/4 3/4
2 3/4 3/4
1 DEE R/W 0
0 LVE R/W 0
unimplemented, read as 0 DEF: Data EEPROM interrupt request flag 0: No request 1: Interrupt request LVF: LVD interrupt request flag 0: No request 1: Interrupt request unimplemented, read as 0 DEE: Data EEPROM Interrupt Control 0: Disable 1: Enable LVE: LVD Interrupt Control 0: Disable 1: Enable
Bit 4
Bit 3~2 Bit 1
Bit 0
Rev. 1.00
111
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
Interrupt Operation When the conditions for an interrupt event occur, such as a TM Comparator P, Comparator A or Comparator B match or A/D conversion completion etc, the relevant interrupt request flag will be set. Whether the request flag actually generates a program jump to the relevant interrupt vector is determined by the condition of the interrupt enable bit. If the enable bit is set high then the program will jump to its relevant vector; if the enable bit is zero then although the interrupt request flag is set an actual interrupt will not be generated and the program will not jump to the relevant interrupt vector. The global interrupt enable bit, if cleared to zero, will disable all interrupts. When an interrupt is generated, the Program Counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. The Program Counter will then be loaded with a new address which will be the value of the corresponding interrupt vector. The microcontroller will then fetch its next instruction from this interrupt vector. The instruction at this vector will usually be a JMP which will jump to another section of program which is known as the interrupt service routine. Here is located the code to control the appropriate interrupt. The interrupt service routine must be terminated with a RETI, which retrieves the original Program Counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred. The various interrupt enable bits, together with their associated request flags, are shown in the accompanying diagrams with their order of priority. Some interrupt sources have their own individual vector while others share the same multi-function interrupt vector. Once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the global interrupt enable bit, EMI bit will be cleared automatically. This will prevent any further interrupt nesting from occurring. However, if other interrupt requests occur during this interval, although the interrupt will not be immediately serviced, the request flag will still be recorded. If an interrupt requires immediate servicing while the program is already in another interrupt service routine, the EMI bit should be set after entering the routine, to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the Stack Pointer is decremented. If immediate service is desired, the stack must be prevented from becoming full. In case of simultaneous requests, the accompanying diagram shows the priority that is applied. All of the interrupt request flags when set will wake-up the device if it is in SLEEP or IDLE Mode, however to prevent a wake-up from occurring the corresponding flag should be set before the device is in SLEEP or IDLE Mode.
Rev. 1.00
112
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
Legend
xxF xxF xxE
Request Flag - no auto reset in ISR Request Flag - auto reset in ISR Enable Bit
EMI auto disabled in ISR Interrupt Request Name Flags INT Pin INTF Enable Bits INTE Master Enable EMI Vector 04H
Priority High
Interrupt Name TM1 P TM1 A TM0 P TM0 A
Request Flags T1PF T1AF T0PF T0AF
Enable Bits T1PE T1AE T0PE T0AE
Comparator
CPF
CPE
EMI
08H
M. Funct. 0
MF0F
MF0E
EMI
0CH
EEPROM
DEF LVF
DEE LVE
M. Funct. 2
MF2F
MF2E
EMI
14H
LVD
A/D
ADF
ADE
EMI
18H
Time Base 0 TB0F Interrupts contained within Multi-Function Interrupts
TB0E
EMI
1CH
Time Base 1 TB1F
TB1E
EMI
20H
Low
Interrupt Structure - HT66F03
Rev. 1.00
113
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
Legend
EMI auto disabled in ISR Interrupt Request Flags Name INT Pin Enable Bits T1PE T1AE T0PE T0AE T2PE T2AE T2BE M. Funct. 1 MF1F MF1E EMI 10H INTF Enable Bits INTE Master Enable EMI Vector 04H
xxF xxF xxE
Request Flag - no auto reset in ISR Request Flag - auto reset in ISR Enable Bit
Priority High
Interrupt Name TM1 P TM1 A TM0 P TM0 A TM2 P TM2 A TM2 B
Request Flags T1PF T1AF T0PF T0AF T2PF T2AF T2BF
Comparator
CPF
CPE
EMI
08H
M. Funct. 0
MF0F
MF0E
EMI
0CH
EEPROM
DEF LVF
DEE LVE
M. Funct. 2
MF2F
MF2E
EMI
14H
LVD
A/D
ADF
ADE
EMI
18H
Time Base 0 TB0F Interrupts contained within Multi-Function Interrupts Time Base 1 TB1F
TB0E TB1E
EMI EMI
1CH 20H Low
Interrupt Structure - HT66F04
Rev. 1.00
114
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
Legend
xxF xxF xxE
Request Flag - no auto reset in ISR Request Flag - auto reset in ISR Enable Bit
EMI auto disabled in ISR Interrupt Request Name Flags INT Pin INTF Enable Bits INTE Master Enable EMI Vector 04H
Priority High
Interrupt Name TM1 P TM1 A TM0 P TM0 A
Request Flags T1PF T1AF T0PF T0AF
Enable Bits T1PE T1AE T0PE T0AE
Comparator
CPF
CPE
EMI
08H
M. Funct. 0
MF0F
MF0E
EMI
0CH
EEPROM
DEF LVF
DEE LVE
M. Funct. 2
MF2F
MF2E
EMI
14H
LVD
Time Base 0 TB0F
TB0E
EMI
1CH
Interrupts contained within Multi-Function Interrupts
Time Base 1 TB1F
TB1E
EMI
20H
Low
Interrupt Structure - HT68F03/HT68F04
Rev. 1.00
115
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
External Interrupt The external interrupt is controlled by signal transitions on the INT pin. An external interrupt request will take place when the external interrupt request flag, INTF, is set, which will occur when a transition, whose type is chosen by the edge select bits, appears on the external interrupt pin. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and respective external interrupt enable bit, INTE, must first be set. Additionally the correct interrupt edge type must be selected using the INTEG register to enable the external interrupt function and to choose the trigger edge type. As the external interrupt pin is pin-shared with I/O pin, it can only be configured as external interrupt pin if the external interrupt enable bit in the corresponding interrupt register has been set. The pin must also be setup as an input by setting the corresponding bit in the port control register. When the interrupt is enabled, the stack is not full and the correct transition type appears on the external interrupt pin, a subroutine call to the external interrupt vector, will take place. When the interrupt is serviced, the external interrupt request flag, INTF, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. Note that any pull-high resistor selections on the external interrupt pin will remain valid even if the pin is used as an external interrupt input. The INTEG register is used to select the type of active edge that will trigger the external interrupt. A choice of either rising or falling or both edge types can be chosen to trigger an external interrupt. Note that the INTEG register can also be used to disable the external interrupt function. Comparator Interrupt The comparator interrupt is controlled by the internal comparator. A comparator interrupt request will take place when the comparator interrupt request flag, CPF, is set, a situation that will occur when the comparator output changes state. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and comparator interrupt enable bit, CPE, must first be set. When the interrupt is enabled, the stack is not full and the comparator inputs generate a comparator output transition, a subroutine call to the comparator interrupt vector, will take place. When the interrupt is serviced, the comparator interrupt request flag, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. Multi-function Interrupt Within these devices there are up to three Multi-function interrupts. Unlike the other independent interrupts, these interrupts have no independent source, but rather are formed from other existing interrupt sources, namely the TM Interrupts, SIM Interrupt, External Peripheral Interrupt, LVD interrupt and EEPROM Interrupt. Rev. 1.00 116 A Multi-function interrupt request will take place when any of the Multi-function interrupt request flags, MFnF are set. The Multi-function interrupt flags will be set when any of their included functions generate an interrupt request flag. To allow the program to branch to its respective interrupt vector address, when the Multi-function interrupt is enabled and the stack is not full, and either one of the interrupts contained within each of Multi-function interrupt occurs, a subroutine call to one of the Multi-function interrupt vectors will take place. When the interrupt is serviced, the related Multi-Function request flag, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. However, it must be noted that, although the Multi-function Interrupt flags will be automatically reset when the interrupt is serviced, the request flags from the original source of the Multi-function interrupts, namely the TM Interrupts, LVD interrupt and EEPROM Interrupt will not be automatically reset and must be manually reset by the application program. A/D Converter Interrupt Some devices contain an A/D converter which has its own independent interrupt. The A/D Converter Interrupt is controlled by the termination of an A/D conversion process. An A/D Converter Interrupt request will take place when the A/D Converter Interrupt request flag, ADF, is set, which occurs when the A/D conversion process finishes. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and A/D Interrupt enable bit, ADE, must first be set. When the interrupt is enabled, the stack is not full and the A/D conversion process has ended, a subroutine call to the A/D Converter Interrupt vector, will take place. When the interrupt is serviced, the A/D Converter Interrupt flag, ADF, will be automatically cleared. The EMI bit will also be automatically cleared to disable other interrupts. Time Base Interrupts The function of the Time Base Interrupts is to provide regular time signal in the form of an internal interrupt. They are controlled by the overflow signals from their respective timer functions. When these happens their respective interrupt request flags, TB0F or TB1F will be set. To allow the program to branch to their respective interrupt vector addresses, the global interrupt enable bit, EMI and Time Base enable bits, TB0E or TB1E, must first be set. When the interrupt is enabled, the stack is not full and the Time Base overflows, a subroutine call to their respective vector locations will take place. When the interrupt is serviced, the respective interrupt request flag, TB0F or TB1F, will be automatically reset and the EMI bit will be cleared to disable other interrupts.
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
The purpose of the Time Base Interrupt is to provide an interrupt signal at fixed time periods. Their clock sources originate from the internal clock source fTB. This fTB input clock passes through a divider, the division ratio of which is selected by programming the appropriate bits in the TBC register to obtain longer interrupt periods whose value ranges. The clock source that generates fTB, which in turn controls the Time Base interrupt period, can originate from several different sources, as shown in the System Operating Mode section.
* TBC Register
Bit Name R/W POR Bit 7
7 TBON R/W 0
6 TBCK R/W 0
5 TB11 R/W 1
4 TB10 R/W 1
3 LXTLP R/W 0
2 TB02 R/W 1
1 TB01 R/W 1
0 TB00 R/W 1
TBON: TB0 and TB1 Control 0: Disable 1: Enable TBCK: Select fTB Clock 0: fTBC 1: fSYS/4 TB11~TB10: Select Time Base 1 Time-out Period 00: 4096/fTB 01: 8192/fTB 10: 16384/fTB 11: 32768/fTB LXTLP: LXT Low Power Control 0: Disable 1: Enable TB02~TB00: Select Time Base 0 Time-out Period 000: 256/fTB 001: 512/fTB 010: 1024/fTB 011: 2048/fTB 100: 4096/fTB 101: 8192/fTB 110: 16384/fTB 111: 32768/fTB
Bit 6
Bit 5~4
Bit 3
Bit 2~0
TB02~TB00 LXT M U L IR C X C o n fig u r a tio n O p tio n fS
YS
/4 M
BC
fT
U X
fT
B
2
8
~2
15
T im e B a s e 0 In te r r u p t
2
12
~2
15
T im e B a s e 1 In te r r u p t
T B C K B it
TB11~TB10
Time Base Interrupt
Rev. 1.00
117
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
EEPROM Interrupt The EEPROM Interrupt, is contained within the Multi-function Interrupt. An EEPROM Interrupt request will take place when the EEPROM Interrupt request flag, DEF, is set, which occurs when an EEPROM Write or Read cycle ends. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, EEPROM Interrupt enable bit, DEE, and associated Multi-function interrupt enable bit, must first be set. When the interrupt is enabled, the stack is not full and an EEPROM Write or Read cycle ends, a subroutine call to the respective Multi-function Interrupt vector, will take place. When the EEPROM Interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts, however only the Multi-function interrupt request flag will be also automatically cleared. As the DEF flag will not be automatically cleared, it has to be cleared by the application program. LVD Interrupt The Low Voltage Detector Interrupt is contained within the Multi-function Interrupt. An LVD Interrupt request will take place when the LVD Interrupt request flag, LVF, is set, which occurs when the Low Voltage Detector function detects a low power supply voltage. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, Low Voltage Interrupt enable bit, LVE, and associated Multi-function interrupt enable bit, must first be set. When the interrupt is enabled, the stack is not full and a low voltage condition occurs, a subroutine call to the Multi-function Interrupt vector, will take place. When the Low Voltage Interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts, however only the Multi-function interrupt request flag will be also automatically cleared. As the LVF flag will not be automatically cleared, it has to be cleared by the application program. TM Interrupts The Compact and Standard Type TMs have two interrupts each, while the Enhanced Type TM has three interrupts. All of the TM interrupts are contained within the Multi-function Interrupts. For each of the Compact and Standard Type TMs there are two interrupt request flags TnPF and TnAF and two enable bits TnPE and TnAE. For the Enhanced Type TM there are three interrupt request flags TnPF, TnAF and TnBF and three enable bits TnPE, TnAE and TnBE. A TM interrupt request will take place when any of the TM request flags are set, a situation which occurs when a TM comparator P, A or B match situation happens. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, respective TM Interrupt enable bit, and relevant Multi-function Interrupt enable bit, MFnE, must first be set. When the interrupt is enabled, the stack is not full and a TM comparator match situation occurs, a subroutine call to the relevant Multi-function Interrupt vector locations, will take place. When the TM interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts, however only the related MFnF flag will be automatically cleared. As the TM interrupt request flags will not be automatically cleared, they have to be cleared by the application program. Interrupt Wake-up Function Each of the interrupt functions has the capability of waking up the microcontroller when in the SLEEP or IDLE Mode. A wake-up is generated when an interrupt request flag changes from low to high and is independent of whether the interrupt is enabled or not. Therefore, even though the device is in the SLEEP or IDLE Mode and its system oscillator stopped, situations such as external edge transitions on the external interrupt pins, a low power supply voltage or comparator input change may cause their respective interrupt flag to be set high and consequently generate an interrupt. Care must therefore be taken if spurious wake-up situations are to be avoided. If an interrupt wake-up function is to be disabled then the corresponding interrupt request flag should be set high before the device enters the SLEEP or IDLE Mode. The interrupt enable bits have no effect on the interrupt wake-up function.
Rev. 1.00
118
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
Programming Considerations By disabling the relevant interrupt enable bits, a requested interrupt can be prevented from being serviced, however, once an interrupt request flag is set, it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request flag is cleared by the application program. Where a certain interrupt is contained within a Multi-function interrupt, then when the interrupt service routine is executed, as only the Multi-function interrupt request flags, MFnF, will be automatically cleared, the individual request flag for the function needs to be cleared by the application program. It is recommended that programs do not use the CALL instruction within the interrupt service subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately. If only one stack is left and the interrupt is not well controlled, the original control sequence will be damaged once a CALL subroutine is executed in the interrupt subroutine. Every interrupt has the capability of waking up the microcontroller when it is in SLEEP or IDLE Mode, the wake up being generated when the interrupt request flag changes from low to high. If it is required to prevent a certain interrupt from waking up the microcontroller then its respective request flag should be first set high before enter SLEEP or IDLE Mode. As only the Program Counter is pushed onto the stack, then when the interrupt is serviced, if the contents of the accumulator, status register or other registers are altered by the interrupt service program, their contents should be saved to the memory at the beginning of the interrupt service routine. To return from an interrupt subroutine, either a RET or RETI instruction may be executed. The RETI instruction in addition to executing a return to the main program also automatically sets the EMI bit high to allow further interrupts. The RET instruction however only executes a return to the main program leaving the EMI bit in its present zero state and therefore disabling the execution of further interrupts.
Rev. 1.00
119
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
Power Down Mode and Wake-up
Entering the IDLE or SLEEP Mode There is only one way for the device to enter the SLEEP or IDLE Mode and that is to execute the HALT instruction in the application program. When this instruction is executed, the following will occur:
* The system clock will be stopped and the application
Wake-up After the system enters the SLEEP or IDLE Mode, it can be woken up from one of various sources listed as follows:
* An external reset * An external falling edge on Port A * A system interrupt * A WDT overflow
program will stop at the HALT instruction.
* The Data Memory contents and registers will maintain
their present condition.
* The WDT will be cleared and resume counting if the
WDT clock source is selected to come from the fSUB clock source and the WDT is enabled. The WDT will stop if its clock source originates from the system clock.
* The I/O ports will maintain their present condition. * In the status register, the Power Down flag, PDF, will be
set and the Watchdog time-out flag, TO, will be cleared. Standby Current Considerations As the main reason for entering the SLEEP or IDLE Mode is to keep the current consumption of the device to as low a value as possible, perhaps only in the order of several micro-amps, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimised. Special attention must be made to the I/O pins on the device. All high-impedance input pins must be connected to either a fixed high or low level as any floating input pins could create internal oscillations and result in increased current consumption. This also applies to devices which have different package types, as there may be unbonbed pins. These must either be setup as outputs or if setup as inputs must have pull-high resistors connected. Care must also be taken with the loads, which are connected to I/O pins, which are setup as outputs. These should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other CMOS inputs. Also note that additional standby current will also be required if the configuration options have enabled the LIRC oscillator.
If the system is woken up by an external reset, the device will experience a full system reset, however, if the device is woken up by a WDT overflow, a Watchdog Timer reset will be initiated. Although both of these wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the TO and PDF flags. The PDF flag is cleared by a system power-up or executing the clear Watchdog Timer instructions and is set when executing the HALT instruction. The TO flag is set if a WDT time-out occurs, and causes a wake-up that only resets the Program Counter and Stack Pointer, the other flags remain in their original status. Each pin on Port A can be setup using the PAWU register to permit a negative transition on the pin to wake-up the system. When a Port A pin wake-up occurs, the program will resume execution at the instruction following the HALT instruction. If the system is woken up by an interrupt, then two possible situations may occur. The first is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the HALT instruction. In this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is finally enabled or when a stack level becomes free. The other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. If an interrupt request flag is set high before entering the SLEEP or IDLE Mode, the wake-up function of the related interrupt will be disabled.
Rev. 1.00
120
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
Low Voltage Detector - LVD
Each device has a Low Voltage Detector function, also known as LVD. This enabled the device to monitor the power supply voltage, VDD, and provide a warning signal should it fall below a certain level. This function may be especially useful in battery applications where the supply voltage will gradually reduce as the battery ages, as it allows an early warning battery low signal to be generated. The Low Voltage Detector also has the capability of generating an interrupt signal. LVD Register The Low Voltage Detector function is controlled using a single register with the name LVDC. Three bits in this register, VLVD2~VLVD0, are used to select one of eight fixed voltages below which a low voltage condition will be detemined. A low voltage condition is indicated when the LVDO bit is set. If the LVDO bit is low, this indicates that the VDD voltage is above the preset low voltage value. The LVDEN bit is used to control the overall on/off function of the low voltage detector. Setting the bit high will enable the low voltage detector. Clearing the bit to zero will switch off the internal low voltage detector circuits. As the low voltage detector will consume a certain amount of power, it may be desirable to switch off the circuit when not in use, an important consideration in power sensitive battery powered applications.
* LVDC Register
Bit Name R/W POR Bit 7~6 Bit 5
7 3/4 3/4 3/4
6 3/4 3/4 3/4
5 LVDO R 0
4 LVDEN R/W 0
3 3/4 3/4 3/4
2 VLVD2 R/W 0
1 VLVD1 R/W 0
0 VLVD0 R/W 0
unimplemented, read as 0 LVDO: LVD Output Flag 0: No Low Voltage Detect 1: Low Voltage Detect LVDEN: Low Voltage Detector Control 0: Disable 1: Enable unimplemented, read as 0 VLVD2 ~ VLVD0: Select LVD Voltage 000: 2.0V 001: 2.2V 010: 2.4V 011: 2.7V 100: 3.0V 101: 3.3V 110: 3.6V 111: 4.4V
Bit
Bit 3 Bit 2~0
Rev. 1.00
121
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
LVD Operation The Low Voltage Detector function operates by comparing the power supply voltage, VDD, with a pre-specified voltage level stored in the LVDC register. This has a range of between 2.0V and 4.4V. When the power supply voltage, VDD, falls below this pre-determined value, the LVDO bit will be set high indicating a low power supply voltage condition. The Low Voltage Detector function is supplied by a reference voltage which will be automatically enabled. When the device is powered down the low voltage detector will remain active if the LVDEN bit is high. After enabling the Low Voltage Detector, a time delay tLVDS should be allowed for the circuitry to stabilise before reading the LVDO bit. Note also that as the VDD voltage may rise and fall rather slowly, at the voltage nears that of VLVD, there may be multiple bit LVDO transitions.
VDD V
LVD
The Low Voltage Detector also has its own interrupt which is contained within one of the Multi-function interrupts, providing an alternative means of low voltage detection, in addition to polling the LVDO bit. The interrupt will only be generated after a delay of tLVD after the LVDO bit has been set high by a low voltage condition. When the device is powered down the Low Voltage Detector will remain active if the LVDEN bit is high. In this case, the LVF interrupt request flag will be set, causing an interrupt to be generated if VDD falls below the preset LVD voltage. This will cause the device to wake-up from the SLEEP or IDLE Mode, however if the Low Voltage Detector wake up function is not required then the LVF flag should be first set high before the device enters the SLEEP or IDLE Mode.
LVDEN LVDO tL
VDS
LVD Operation
Rev. 1.00
122
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
Configuration Options
Configuration options refer to certain options within the MCU that are programmed into the device during the programming process. During the development process, these options are selected using the HT-IDE software development tools. As these options are programmed into the device using the hardware programming tools, once they are selected they cannot be changed later using the application program. All options must be defined for proper system function, the details of which are shown in the table. No. Oscillator Options High Speed/Low Speed System Oscillator Selection - fOSC: 1. HXT + LIRC 2. ERC + LIRC 3. HIRC + LIRC 4. HIRC + LXT WDT Clock Selection - fS: 1. fSUB 2. fSYS/4 HIRC Frequency Selection: 1. 4MHz 2. 8MHz 3. 12MHz Options
1
2
3
Note: The fSUB and the fTBC clock source are LXT or LIRC selection by the fOSC configuration option. Reset Pin Options 4 PA7/RES Pin Options: 1. RES pin 2. I/O pin
Watchdog Options 5 Watchdog Timer Function: 1. Enable 2. Disable CLRWDT Instructions Selection: 1. 1 instructions 2. 2 instructions
6
LVR Options 7 LVR Function: 1. Enable 2. Disable LVR Voltage Selection: 1. 2.10V 2. 2.55V 3. 3.15V 4. 4.20V
8
Rev. 1.00
123
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
Application Circuits
HT66F03/HT66F04
V 0 .0 1 m F * *
DD
VDD Reset C ir c u it RES AN 0~AN 3 PA0~PA4 VSS
0 .1 m F
1N4148*
10kW ~ 100kW 300W *
0 .1 ~ 1 m F
OSC C ir c u it S e e O s c illa to r S e c tio n
OSC1 OSC2
Note:
* Recommended component for added ESD protection. ** Recommended component in environments where power line noise is significant.
HT68F03/HT68F04
V 0 .0 1 m F * *
DD
VDD Reset C ir c u it RES PA0~PA4 VSS
0 .1 m F
1N4148*
10kW ~ 100kW 300W *
0 .1 ~ 1 m F
OSC C ir c u it S e e O s c illa to r S e c tio n
OSC1 OSC2
Note:
* Recommended component for added ESD protection. ** Recommended component in environments where power line noise is significant.
Rev. 1.00
124
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
Instruction Set
Introduction C e n t ra l t o t he s uc c es s f ul oper a t i on o f a n y microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to perform certain operations. In the case of Holtek microcontroller, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. For easier understanding of the various instruction codes, they have been subdivided into several functional groupings. Instruction Timing Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are required. One instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8MHz system oscillator, most instructions would be implemented within 0.5ms and branch or call instructions would be implemented within 1ms. Although instructions which require one more cycle to implement are generally limited to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions which involve manipulation of the Program Counter Low register or PCL will also take one more cycle to implement. As instructions which change the contents of the PCL will imply a direct jump to that new address, one more cycle will be required. Examples of such instructions would be CLR PCL or MOV PCL, A. For the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. Moving and Transferring Data The transfer of data within the microcontroller program is one of the most frequently used operations. Making use of three kinds of MOV instructions, data can be transferred from registers to the Accumulator and vice-versa as well as being able to move specific immediate data directly into the Accumulator. One of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. Arithmetic Operations The ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller a p p l i c at i o n s . W i t h i n t h e H o l t e k microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for subtraction. The increment and decrement instructions INC, INCA, DEC and DECA provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. Logical and Rotate Operations The standard logical operations such as AND, OR, XOR and CPL all have their own instruction within the Holtek microcontroller instruction set. As with the case of most instructions involving data manipulation, data must pass through the Accumulator which may involve additional programming steps. In all logical data operations, the zero flag may be set if the result of the operation is zero. Another form of logical data manipulation comes from the rotate instructions such as RR, RL, RRC and RLC which provide a simple means of rotating one bit right or left. Different rotate instructions exist depending on program requirements. Rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the Carry bit from where it can be examined and the necessary serial bit set high or low. Another application where rotate data operations are used is to implement multiplication and division calculations. Branches and Control Transfer Program branching takes the form of either jumps to specified locations using the JMP instruction or to a subroutine using the CALL instruction. They differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the subroutine has been carried out. This is done by placing a return instruction RET in the subroutine which will cause the program to jump back to the address right after the CALL instruction. In the case of a JMP instruction, the program simply jumps to the desired location. There is no requirement to jump back to the original jumping off point as in the case of the CALL instruction. One special and extremely useful set of branch instructions are the conditional branches. Here a decision is first made regarding the condition of a certain data memory or individual bits. Depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. These instructions are the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits.
Rev. 1.00
125
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
Bit Operations The ability to provide single bit operations on Data Memory is an extremely flexible feature of all Holtek microcontrollers. This feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the SET [m].i or CLR [m].i instructions respectively. The feature removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. This read-modify-write process is taken care of automatically when these bit operation instructions are used. Table Read Operations Data storage is normally implemented by using registers. However, when working with large amounts of fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data Memory. To overcome this problem, Holtek microcontrollers allow an area of Program Memory to be setup as a table where data can be directly stored. A set of easy to use instructions provides the means by which this fixed data can be referenced and retrieved from the Program Memory. Other Operations In addition to the above functional instructions, a range of other instructions also exist such as the HALT instruction for Power-down operations and instructions to control the operation of the Watchdog Timer for reliable program operations under extreme electric or electromagnetic environments. For their relevant operations, refer to the functional related sections. Instruction Set Summary The following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. Table conventions: x: Bits immediate data m: Data Memory address A: Accumulator i: 0~7 number of bits addr: Program memory address
Mnemonic Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m]
Description
Cycles
Flag Affected
Add Data Memory to ACC Add ACC to Data Memory Add immediate data to ACC Add Data Memory to ACC with Carry Add ACC to Data memory with Carry Subtract immediate data from the ACC Subtract Data Memory from ACC Subtract Data Memory from ACC with result in Data Memory Subtract Data Memory from ACC with Carry Subtract Data Memory from ACC with Carry, result in Data Memory Decimal adjust ACC for Addition with result in Data Memory
1 1Note 1 1 1Note 1 1 1Note 1 1Note 1Note
Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV C
Logic Operation AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] Logical AND Data Memory to ACC Logical OR Data Memory to ACC Logical XOR Data Memory to ACC Logical AND ACC to Data Memory Logical OR ACC to Data Memory Logical XOR ACC to Data Memory Logical AND immediate Data to ACC Logical OR immediate Data to ACC Logical XOR immediate Data to ACC Complement Data Memory Complement Data Memory with result in ACC 1 1 1 1Note 1Note 1Note 1 1 1 1Note 1 Z Z Z Z Z Z Z Z Z Z Z
Increment & Decrement INCA [m] INC [m] DECA [m] DEC [m] Increment Data Memory with result in ACC Increment Data Memory Decrement Data Memory with result in ACC Decrement Data Memory 1 1Note 1 1Note Z Z Z Z
Rev. 1.00
126
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
Mnemonic Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Data Move MOV A,[m] MOV [m],A MOV A,x Bit Operation CLR [m].i SET [m].i Branch JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Table Read TABRD [m] TABRDL [m] Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT Note: No operation Clear Data Memory Set Data Memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of Data Memory Swap nibbles of Data Memory with result in ACC Enter power down mode 1 1Note 1Note 1 1 1 1Note 1 1 None None None TO, PDF TO, PDF TO, PDF None None TO, PDF Read table to TBLH and Data Memory Read table (last page) to TBLH and Data Memory 2note 2Note None None Jump unconditionally Skip if Data Memory is zero Skip if Data Memory is zero with data movement to ACC Skip if bit i of Data Memory is zero Skip if bit i of Data Memory is not zero Skip if increment Data Memory is zero Skip if decrement Data Memory is zero Skip if increment Data Memory is zero with result in ACC Skip if decrement Data Memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt 2 1Note 1note 1Note 1Note 1Note 1Note 1Note 1Note 2 2 2 2 None None None None None None None None None None None None None Clear bit of Data Memory Set bit of Data Memory 1Note 1Note None None Move Data Memory to ACC Move ACC to Data Memory Move immediate data to ACC 1 1Note 1 None None None Rotate Data Memory right with result in ACC Rotate Data Memory right Rotate Data Memory right through Carry with result in ACC Rotate Data Memory right through Carry Rotate Data Memory left with result in ACC Rotate Data Memory left Rotate Data Memory left through Carry with result in ACC Rotate Data Memory left through Carry 1 1Note 1 1Note 1 1Note 1 1Note None None C C None None C C Description Cycles Flag Affected
1. For skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution. 3. For the CLR WDT1 and CLR WDT2 instructions the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after both CLR WDT1 and CLR WDT2 instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged.
Rev. 1.00
127
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
Instruction Definition
ADC A,[m] Description Operation Affected flag(s) ADCM A,[m] Description Operation Affected flag(s) ADD A,[m] Description Operation Affected flag(s) ADD A,x Description Operation Affected flag(s) ADDM A,[m] Description Operation Affected flag(s) AND A,[m] Description Operation Affected flag(s) AND A,x Description Operation Affected flag(s) ANDM A,[m] Description Operation Affected flag(s) Rev. 1.00 Add Data Memory to ACC with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the Accumulator. ACC ACC + [m] + C OV, Z, AC, C Add ACC to Data Memory with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory. [m] ACC + [m] + C OV, Z, AC, C Add Data Memory to ACC The contents of the specified Data Memory and the Accumulator are added. The result is stored in the Accumulator. ACC ACC + [m] OV, Z, AC, C Add immediate data to ACC The contents of the Accumulator and the specified immediate data are added. The result is stored in the Accumulator. ACC ACC + x OV, Z, AC, C Add ACC to Data Memory The contents of the specified Data Memory and the Accumulator are added. The result is stored in the specified Data Memory. [m] ACC + [m] OV, Z, AC, C Logical AND Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator. ACC ACC AND [m] Z Logical AND immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical AND operation. The result is stored in the Accumulator. ACC ACC AND x Z Logical AND ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory. [m] ACC AND [m] Z 128 April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
CALL addr Description Subroutine call Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the stack. The specified address is then loaded and the program continues execution from this new address. As this instruction requires an additional operation, it is a two cycle instruction. Stack Program Counter + 1 Program Counter addr None Clear Data Memory Each bit of the specified Data Memory is cleared to 0. [m] 00H None Clear bit of Data Memory Bit i of the specified Data Memory is cleared to 0. [m].i 0 None Clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. WDT cleared TO 0 PDF 0 TO, PDF Pre-clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Repetitively executing this instruction without alternately executing CLR WDT2 will have no effect. WDT cleared TO 0 PDF 0 TO, PDF Pre-clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Repetitively executing this instruction without alternately executing CLR WDT1 will have no effect. WDT cleared TO 0 PDF 0 TO, PDF
Operation
Affected flag(s) CLR [m] Description Operation Affected flag(s) CLR [m].i Description Operation Affected flag(s) CLR WDT Description Operation
Affected flag(s) CLR WDT1 Description
Operation
Affected flag(s) CLR WDT2 Description
Operation
Affected flag(s)
Rev. 1.00
129
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
CPL [m] Description Operation Affected flag(s) CPLA [m] Description Complement Data Memory Each bit of the specified Data Memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice versa. [m] [m] Z Complement Data Memory with result in ACC Each bit of the specified Data Memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC [m] Z Decimal-Adjust ACC for addition with result in Data Memory Convert the contents of the Accumulator value to a BCD ( Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag may be affected by this instruction which indicates that if the original BCD sum is greater than 100, it allows multiple precision decimal addition. [m] ACC + 00H or [m] ACC + 06H or [m] ACC + 60H or [m] ACC + 66H C Decrement Data Memory Data in the specified Data Memory is decremented by 1. [m] [m] - 1 Z Decrement Data Memory with result in ACC Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC [m] - 1 Z Enter power down mode This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. TO 0 PDF 1 TO, PDF
Operation Affected flag(s) DAA [m] Description
Operation
Affected flag(s) DEC [m] Description Operation Affected flag(s) DECA [m] Description Operation Affected flag(s) HALT Description
Operation
Affected flag(s)
Rev. 1.00
130
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
INC [m] Description Operation Affected flag(s) INCA [m] Description Operation Affected flag(s) JMP addr Description Increment Data Memory Data in the specified Data Memory is incremented by 1. [m] [m] + 1 Z Increment Data Memory with result in ACC Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC [m] + 1 Z Jump unconditionally The contents of the Program Counter are replaced with the specified address. Program execution then continues from this new address. As this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. Program Counter addr None Move Data Memory to ACC The contents of the specified Data Memory are copied to the Accumulator. ACC [m] None Move immediate data to ACC The immediate data specified is loaded into the Accumulator. ACC x None Move ACC to Data Memory The contents of the Accumulator are copied to the specified Data Memory. [m] ACC None No operation No operation is performed. Execution continues with the next instruction. No operation None Logical OR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ACC OR [m] Z
Operation Affected flag(s) MOV A,[m] Description Operation Affected flag(s) MOV A,x Description Operation Affected flag(s) MOV [m],A Description Operation Affected flag(s) NOP Description Operation Affected flag(s) OR A,[m] Description Operation Affected flag(s)
Rev. 1.00
131
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
OR A,x Description Operation Affected flag(s) ORM A,[m] Description Operation Affected flag(s) RET Description Operation Affected flag(s) RET A,x Description Operation Logical OR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ACC OR x Z Logical OR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory. [m] ACC OR [m] Z Return from subroutine The Program Counter is restored from the stack. Program execution continues at the restored address. Program Counter Stack None Return from subroutine and load immediate data to ACC The Program Counter is restored from the stack and the Accumulator loaded with the specified immediate data. Program execution continues at the restored address. Program Counter Stack ACC x None Return from interrupt The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program. Program Counter Stack EMI 1 None Rotate Data Memory left The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. [m].(i+1) [m].i; (i = 0~6) [m].0 [m].7 None Rotate Data Memory left with result in ACC The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) [m].i; (i = 0~6) ACC.0 [m].7 None
Affected flag(s) RETI Description
Operation
Affected flag(s) RL [m] Description Operation
Affected flag(s) RLA [m] Description
Operation
Affected flag(s)
Rev. 1.00
132
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
RLC [m] Description Operation Rotate Data Memory left through Carry The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into bit 0. [m].(i+1) [m].i; (i = 0~6) [m].0 C C [m].7 C Rotate Data Memory left through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) [m].i; (i = 0~6) ACC.0 C C [m].7 C Rotate Data Memory right The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7. [m].i [m].(i+1); (i = 0~6) [m].7 [m].0 None Rotate Data Memory right with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i [m].(i+1); (i = 0~6) ACC.7 [m].0 None Rotate Data Memory right through Carry The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. [m].i [m].(i+1); (i = 0~6) [m].7 C C [m].0 C Rotate Data Memory right through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i [m].(i+1); (i = 0~6) ACC.7 C C [m].0 C
Affected flag(s) RLCA [m] Description
Operation
Affected flag(s) RR [m] Description Operation
Affected flag(s) RRA [m] Description
Operation
Affected flag(s) RRC [m] Description Operation
Affected flag(s) RRCA [m] Description
Operation
Affected flag(s)
Rev. 1.00
133
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
SBC A,[m] Description Subtract Data Memory from ACC with Carry The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ACC - [m] - C OV, Z, AC, C Subtract Data Memory from ACC with Carry and result in Data Memory The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ACC - [m] - C OV, Z, AC, C Skip if decrement Data Memory is 0 The contents of the specified Data Memory are first decremented by 1. If the result is 0 the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] [m] - 1 Skip if [m] = 0 None Skip if decrement Data Memory is zero with result in ACC The contents of the specified Data Memory are first decremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. ACC [m] - 1 Skip if ACC = 0 None Set Data Memory Each bit of the specified Data Memory is set to 1. [m] FFH None Set bit of Data Memory Bit i of the specified Data Memory is set to 1. [m].i 1 None
Operation Affected flag(s) SBCM A,[m] Description
Operation Affected flag(s) SDZ [m] Description
Operation Affected flag(s) SDZA [m] Description
Operation
Affected flag(s) SET [m] Description Operation Affected flag(s) SET [m].i Description Operation Affected flag(s)
Rev. 1.00
134
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
SIZ [m] Description Skip if increment Data Memory is 0 The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] [m] + 1 Skip if [m] = 0 None Skip if increment Data Memory is zero with result in ACC The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC [m] + 1 Skip if ACC = 0 None Skip if bit i of Data Memory is not 0 If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction. Skip if [m].i 0 None Subtract Data Memory from ACC The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ACC - [m] OV, Z, AC, C Subtract Data Memory from ACC with result in Data Memory The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ACC - [m] OV, Z, AC, C Subtract immediate data from ACC The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ACC - x OV, Z, AC, C
Operation Affected flag(s) SIZA [m] Description
Operation Affected flag(s) SNZ [m].i Description
Operation Affected flag(s) SUB A,[m] Description
Operation Affected flag(s) SUBM A,[m] Description
Operation Affected flag(s) SUB A,x Description
Operation Affected flag(s)
Rev. 1.00
135
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
SWAP [m] Description Operation Affected flag(s) SWAPA [m] Description Operation Swap nibbles of Data Memory The low-order and high-order nibbles of the specified Data Memory are interchanged. [m].3~[m].0 [m].7 ~ [m].4 None Swap nibbles of Data Memory with result in ACC The low-order and high-order nibbles of the specified Data Memory are interchanged. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC.3 ~ ACC.0 [m].7 ~ [m].4 ACC.7 ~ ACC.4 [m].3 ~ [m].0 None Skip if Data Memory is 0 If the contents of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Skip if [m] = 0 None Skip if Data Memory is 0 with data movement to ACC The contents of the specified Data Memory are copied to the Accumulator. If the value is zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC [m] Skip if [m] = 0 None Skip if bit i of Data Memory is 0 If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. Skip if [m].i = 0 None Read table to TBLH and Data Memory The program code addressed by the table pointer (TBHP and TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] program code (low byte) TBLH program code (high byte) None Read table (last page) to TBLH and Data Memory The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] program code (low byte) TBLH program code (high byte) None
Affected flag(s) SZ [m] Description
Operation Affected flag(s) SZA [m] Description
Operation Affected flag(s) SZ [m].i Description
Operation Affected flag(s) TABRD [m] Description Operation
Affected flag(s) TABRDL [m] Description Operation
Affected flag(s)
Rev. 1.00
136
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
XOR A,[m] Description Operation Affected flag(s) XORM A,[m] Description Operation Affected flag(s) XOR A,x Description Operation Affected flag(s) Logical XOR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ACC XOR [m] Z Logical XOR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory. [m] ACC XOR [m] Z Logical XOR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ACC XOR x Z
Rev. 1.00
137
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
Package Information
10-pin MSOP Outline Dimensions
10
6 E1
1
5
D L A2 A e R 0 .1 0 B (4 C O R N E R S ) A1 C
E
q
L1
Symbol A A1 A2 B C D E E1 e L L1 q
Dimensions in mm Min. 3/4 0.00 0.75 0.17 3/4 3/4 3/4 3/4 3/4 0.4 3/4 0 Nom. 3/4 3/4 3/4 3/4 3/4 3.0 4.9 3.0 0.5 3/4 0.95 3/4 Max. 1.10 0.15 0.95 0.27 0.25 3/4 3/4 3/4 3/4 0.8 3/4 8
Rev. 1.00
138
April 16, 2010
HT66F03/HT66F04/HT68F03/HT68F04
Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shenzhen Sales Office) 5F, Unit A, Productivity Building, No.5 Gaoxin M 2nd Road, Nanshan District, Shenzhen, China 518057 Tel: 86-755-8616-9908, 86-755-8616-9308 Fax: 86-755-8616-9722 Holtek Semiconductor (USA), Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, CA 94538, USA Tel: 1-510-252-9880 Fax: 1-510-252-9885 http://www.holtek.com
Copyright O 2010 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holteks products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
Rev. 1.00
139
April 16, 2010

▲Up To Search▲

Price & Availability of HT66F03

	To Download HT66F03 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .